公开(公告)号：WO2005091480A1

公开(公告)日：2005-09-29

申请号：PCT/EP2005/050848

申请日：2005-02-28

Applicant: STMICROELECTRONICS s.r.l. ,  ADRAGNA, Claudio ,  FAGNANI, Mauro ,  MORICONI, Ugo

Inventor： ADRAGNA, Claudio ,  FAGNANI, Mauro ,  MORICONI, Ugo

IPC: H02M1/00

CPC classification number: H02M1/32 ,  H02M1/4225 ,  Y02B70/126

Abstract: There is described a device for the correction of the power factor in forced switching power supplies. The device comprises a converter (20) and a control device (100) coupled with the converter (20) in order to obtain from an alternated mains input voltage (Vin) a regulated voltage (Vout) on the output terminal; the converter (20) comprises a power transistor (M) and said control device (100) comprises an error amplifier (3) having in input on the inverting terminal a signal (Vr) proportional to the regulated voltage (Vout) and on the non-inverting terminal a reference voltage (Vref). The signal (Vr) proportional to the regulated voltage is produced by a first resistance (R1) and a second resistance (R2) coupled in series to which is applied said regulated voltage (Vout); a terminal of the second resistance (R2) is connected with the inverting terminal of the error amplifier (3). The device for the correction of the power factor comprises first means (D50) positioned between the first resistance (RI) and the inverting terminal of the error amplifier (3) and second means (50) suitable for detecting the electrical connection of the first means (D50) with the output terminal of said device for the correction of the power factor and suitable for detecting an output signal (Vr2) of the second resistance (R2). The second means (50) are suitable for supplying a malfunction signal (Fault) of the device for the correction of the power factor when the second means (50) detect electric disconnection of the first means (D50) from said output terminal (Out) or when the output signal (Vr2) of the second resistance (R2) tends to zero.

Abstract translation: 描述了用于在强制开关电源中校正功率因数的装置。 该装置包括与转换器（20）耦合的转换器（20）和控制装置（100），以便从输出端子上的交流电源输入电压（Vin）获得调节电压（Vout）; 所述转换器（20）包括功率晶体管（M），并且所述控制装置（100）包括误差放大器（3），所述误差放大器（3）在反相端子上具有与调节电压（Vout）成比例的信号（Vr） - 反相端子参考电压（Vref）。 与调节电压成比例的信号（Vr）由与所述调节电压（Vout）一起施加的串联耦合的第一电阻（R1）和第二电阻（R2）产生; 第二电阻（R2）的端子与误差放大器（3）的反相端连接。 用于校正功率因数的装置包括位于误差放大器（3）的第一电阻（RI）和反相端之间的第一装置（D50）和第二装置（50），适于检测第一装置 （D50）与所述装置的输出端子进行功率因数的校正，并适于检测第二电阻（R2）的输出信号（Vr2）。 第二装置（50）适用于当第二装置（50）检测到第一装置（D50）从所述输出端子（Out）的电断开时，提供用于校正功率因数的装置的故障信号（Fault） 或者当第二电阻（R2）的输出信号（Vr2）变为零时。

公开(公告)号：WO2005083896A1

公开(公告)日：2005-09-09

申请号：PCT/IB2005/000121

申请日：2005-01-14

Applicant: STMICROELECTRONICS S.R.L. ,  RIMI, Francesco ,  SERRATORE, Alberto ,  AVELLONE, Giuseppe ,  PAPPALARDO, Francesco ,  GALLUZZO, Agostino

Inventor： RIMI, Francesco ,  SERRATORE, Alberto ,  AVELLONE, Giuseppe ,  PAPPALARDO, Francesco ,  GALLUZZO, Agostino

IPC: H04B1/707

CPC classification number: H04B1/7083 ,  H04B1/70735 ,  H04B2201/7071

Abstract: In order to perform, according to a received signal (r), a channel-estimation procedure and a cell-search procedure in cellular communication systems, there are executed at least one first operation of correlation of said received signal (r) with secondary synchronization codes (SSC) and a second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS), whilst said channel-estimation procedure comprises a third operation of correlation of at least part of said received signal (r) with known midamble codes (mid, MPL, MPS), said first, second, and third correlation operation being executed by sending at least part (e mídamble )of said received signal (r) to an input of a correlation bank (111, 151; 203, 253; 303). There are envisaged the operations of: - sending, in a first time interval, the received signal (r) to said correlation bank (303) for executing the first operation of correlation of said received signal (r) with secondary synchronization codes (SSC); - sending, in a second time interval, at least part (e mídamble ) of said received signal (r) to said same correlation bank (303) for executing the second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS); - sending, in a second time interval, the received signal (r) to said same correlation bank (303) for executing the third operation of correlation of at least part (e midamble ) of said received signal (r) with known midamble codes (mid, MPL, MPS). Preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.

Abstract translation: 为了根据接收到的信号（r）执行蜂窝通信系统中的信道估计过程和小区搜索过程，执行所述接收信号（r）与辅助同步的相关的至少一个第一操作 代码（SSC）和所述接收信号（r）与已知中间码（mid，MPL，MPS）的相关的第二操作，而所述信道估计过程包括所述接收信号的至少一部分 所述第一，第二和第三相关操作是通过将所述接收信号（r）的至少一部分（emídamble）发送到相关库（111，...）的输入， 151; 203,253; 303）。 设想了以下操作： - 在第一时间间隔中将接收信号（r）发送到所述相关库（303），以执行所述接收信号（r）与辅同步码（SSC）的相关性的第一操作， ; - 在第二时间间隔中将所述接收信号（r）的至少一部分（emídamble）发送到所述相关相关库（303），用于执行所述接收信号（r）与已知中间码（mid）的相关性的第二操作 ，MPL，MPS）; - 接收信号（r）在第二时间间隔发送到所述相关相关库（303），用于执行所述接收信号（r）的至少部分（emidamble）与已知中间码（中间码）的中间相关的第三操作 ，MPL，MPS）。 优先应用在基于UMTS，CDMA2000，IS95或WBCDMA等标准的移动通信系统中。

公开(公告)号：WO2004003883A1

公开(公告)日：2004-01-08

申请号：PCT/EP2003/006639

申请日：2003-06-23

Applicant: STMICROELECTRONICS S.R.L. ,  DORA S.P.A. ,  PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

Inventor： PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

IPC: G09G3/36

CPC classification number: G09G3/3681 ,  G09G3/3674

Abstract: The present invention describes a system for driving rows of a liquid crystal display comprising at least one module (10) for driving one single row of the liquid crystal display. The module comprises an inverter (T11-T12) operating in a supply path between a first (21) and a second (22) supply line of the system, where the first supply line (21) comprises first means (S1) capable of connecting it to a first (VLCD) or to a second (VA) supply voltage and the second supply line (22) comprises second means (S2) capable of connecting it to a third (VB) or to a fourth (VSS) supply voltage. The inverter (T11-T12) is driven by a logic circuitry (11-12) and sends in output (OUT) a drive signal for one single row of the liquid crystal display.

Abstract translation: 本发明描述了一种用于驱动液晶显示器行的系统，包括用于驱动液晶显示器的一行的至少一个模块（10）。 该模块包括在系统的第一（21）和第二（22）电源线之间的供应路径中工作的逆变器（T11-T12），其中第一供电线（21）包括能够连接的第一装置（S1） 第二电源线（22）包括能够将其连接到第三（VB）或第四（VSS）电源电压的第二装置（S2）。 逆变器（T11-T12）由逻辑电路（11-12）驱动，并向输出（OUT）发送一行液晶显示器的驱动信号。

公开(公告)号：WO2004003882A1

公开(公告)日：2004-01-08

申请号：PCT/EP2003/006638

申请日：2003-06-23

Applicant: STMICROELECTRONICS S.R.L. ,  DORA S.P.A. ,  PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

Inventor： PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G09G2330/021

Abstract: The present invention refers to a system for driving columns of a liquid crystal display comprising a logic circuitry (10) operating in a supply path between a first (VDD) and a second (VSS) supply voltage in which the first supply voltage is (VDD) higher than the second supply voltage (VSS). The logic circuitry (10) is capable of generating starting from the first logic signals (LOW_FRAME, WHITE_PIX) in input second logic signals (CP, CN, CP_N, CN_N) in output whose value is equal to the first (VDD) or second (VSS) supply voltage. The device comprises two elevator devices (11, 12) coupled to the logic circuitry (10) and operating in a supply path between a third supply voltage (VLCD) greater than the first supply voltage (VDD) and the second supply voltage (VSS); the elevator devices (11, 12) are capable of raising the value of the second logic signals (CP, CN, CP_N, CN_N). The device also comprises a first (T11-T12) and a second (T13-T14) pair of transistors shaving different supply paths (VLCD-VA, VB-VSS) and having an output terminal (OUT) in common; the first (T11-T12) and the second (T13-T14) pair of transistors are connected to the elevator devices (11, 12) so as to determine the drive signal of a column. The device comprises turnoff circuitry (15) operating in a supply path between the third (VLCD) and the second supply voltage (VSS) and coupled to the two elevator devices (11, 12). The circuitry (15) is capable of keeping one of the two pairs of transistors (T11-T12, T13-T14) in a turnoff state in the period of time of a frame when the other of the two pairs of transistors (T11-T12, T13-T14) is in operative conditions.

Abstract translation: 本发明涉及一种用于驱动液晶显示器列的系统，其包括在第一电源电压（VDD）和第二（VSS）电源电压之间的供电路径中工作的逻辑电路（10），其中第一电源电压为（VDD ）高于第二电源电压（VSS）。 逻辑电路（10）能够从其值等于第一（VDD）或第二（VDD）的输出中的输入第二逻辑信号（CP，CN，CP_N，CN_N）中的第一逻辑信号（LOW_FRAME，WHITE_PIX） VSS）电源电压。 该装置包括耦合到逻辑电路（10）并且在大于第一电源电压（VDD）和第二电源电压（VSS））的第三电源电压（VLCD）之间的供电路径中操作的两个电梯装置（11,12） ; 电梯装置（11,12）能够提高第二逻辑信号（CP，CN，CP_N，CN_N）的值。 该器件还包括共用剃须不同电源路径（VLCD-VA，VB-VSS）并具有输出端（OUT）的第一（T11-T12）和第二（T13-T14）对晶体管; 第一（T11-T12）和第二（T13-T14）晶体管对连接到电梯装置（11,12），以便确定列的驱动信号。 该装置包括在第三（VLCD）和第二电源电压（VSS）之间的供应路径中工作并耦合到两个电梯装置（11,12）的关闭电路（15）。 当两对晶体管（T11-T12）中的另一对晶体管（T11-T12）的一对晶体管（T11-T12-T12）中的另一个晶体管 ，T13-T14）处于工作状态。

公开(公告)号：WO2002086965A1

公开(公告)日：2002-10-31

申请号：PCT/IT2001/000192

申请日：2001-04-19

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMBRANO, Raffaele ,  ARTONI, Cesare ,  CORVASCE, Chiara

Inventor： ZAMBRANO, Raffaele ,  ARTONI, Cesare ,  CORVASCE, Chiara

IPC: H01L21/8246

CPC classification number: H01L27/11502 ,  H01L21/76877

Abstract: An integrated device having: a first conductive region (6A); a second conductive region (11A); an insulating layer (9) arranged between the first and the second conductive region; at least one through opening (36) extending in said insulating layer (9) between the first and the second conductive region; and a contact structure (10A) formed in the through opening and electrically connecting the first conductive region (6A) and the second conductive region (11B). The contact structure (10A) is formed by a conductive material layer (30) that coats the side surface and the bottom of the through opening (36) and surrounds an empty region (35) which is closed at the top by the second conductive region (11A). The conductive material layer (30) preferably comprises a titanium layer (31) and a titanium-nitride layer (32) arranged on top of one another.

Abstract translation: 一种集成装置，具有：第一导电区域（6A）; 第二导电区域（11A）; 布置在第一和第二导电区域之间的绝缘层（9）; 在所述绝缘层（9）中在所述第一和第二导电区域之间延伸的至少一个通孔（36）; 以及形成在所述通孔中并电连接所述第一导电区域（6A）和所述第二导电区域（11B）的接触结构（10A）。 接触结构（10A）由涂覆贯通孔（36）的侧面和底部的导电性材料层（30）形成，并且包围由第二导电区域在顶部封闭的空区域（35） （11A）。 导电材料层（30）优选地包括彼此顶部布置的钛层（31）和氮化钛层（32）。

公开(公告)号：WO2022144636A1

公开(公告)日：2022-07-07

申请号：PCT/IB2021/061355

申请日：2021-12-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： MASSASCUSA, Sofia ,  FOLLERO, Giulio ,  ALFARANO, Marco

IPC: G06F8/76 ,  H04W12/30 ,  G06F21/71 ,  H04W8/20

Abstract: A method includes compiling, by a compiler (305) of a Smart Secure Platform (SSP) supporting a Primary Platform (105) and a Secondary Platform, source code comprising an implementation of an operating system of the Secondary Platform and applications of the Secondary Platform, to produce compiled source code compatible by an operating system of the Primary Platform (105); linking, by the compiler (305), personalization data to the compiled source code to produce a native Secondary Platform Bundle (SPB) compatible with the Primary Platform (105), the personalization data being associated with a subscription of a user of the SSP; and delivering, by the compiler, the native SPB.

公开(公告)号：WO2014006570A8

公开(公告)日：2014-01-09

申请号：PCT/IB2013/055430

申请日：2013-07-02

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  MOTTA, Alessandro ,  LOI, Sara

IPC: G02B6/12 ,  G02B6/43

Abstract: An integrated electronic device, delimited by a first surface (S 1 ) and by a second surface (S 2 ) and including: a body (2) made of semiconductor material, formed inside which is at least one optoelectronic component chosen between a detector (30) and an emitter (130); and an optical path (OP), which is at least in part of a guided type and extends between the first surface and the second surface, the optical path traversing the body. The optoelectronic component is optically coupled, through the optical path, to a first portion of free space and a second portion of free space, which are arranged, respectively, above and underneath the first and second surfaces.

公开(公告)号：WO2013128480A9

公开(公告)日：2013-09-06

申请号：PCT/IT2012/000060

申请日：2012-02-28

Applicant: STMICROELECTRONICS S.R.L. ,  MURABITO Domenico ,  SAGGIO Mario Giuseppe

Inventor： MURABITO Domenico ,  SAGGIO Mario Giuseppe

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/08 ,  H01L21/02 ,  H01L21/336

Abstract: A vertical-conduction electronic device (100; 150), comprising: a semiconductor wafer (1) including a semiconductor layer (2, 3) having a first side (3a), a first type of conductivity (N), and a first doping level; a first body region (32) and a second body region (34), which have a second type of conductivity (P) and extend in the semiconductor layer (2, 3); an enriched region (12), having the first type of conductivity and a second doping " level higher than the first doping level, which extends in the semiconductor layer facing the first side (3a), between the first and second body regions (32, 34); a dielectric filling region (20), which extends in the semiconductor layer, facing the first side (3a), and completely surrounded by the enriched region (12); and a gate structure (29), which extends on the first side (3a) on the enriched region (12), on the dielectric filling region (20), on part of the first body region (32), and on part of the second body region (34).

公开(公告)号：WO2013128480A1

公开(公告)日：2013-09-06

申请号：PCT/IT2012/000060

申请日：2012-02-28

Applicant: STMICROELECTRONICS S.R.L. ,  MURABITO Domenico ,  SAGGIO Mario Giuseppe

Inventor： MURABITO Domenico ,  SAGGIO Mario Giuseppe

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/08 ,  H01L21/02 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7395

Abstract: A vertical-conduction electronic device (100; 150), comprising: a semiconductor wafer (1) including a semiconductor layer (2, 3) having a first side (3a), a first type of conductivity (N), and a first doping level; a first body region (32) and a second body region (34), which have a second type of conductivity (P) and extend in the semiconductor layer (2, 3); an enriched region (12), having the first type of conductivity and a second doping " level higher than the first doping level, which extends in the semiconductor layer facing the first side (3a), between the first and second body regions (32, 34); a dielectric filling region (20), which extends in the semiconductor layer, facing the first side (3a), and completely surrounded by the enriched region (12); and a gate structure (29), which extends on the first side (3a) on the enriched region (12), on the dielectric filling region (20), on part of the first body region (32), and on part of the second body region (34).

Abstract translation: 一种垂直导电电子器件（100; 150），包括：半导体晶片（1），包括具有第一侧（3a），第一导电类型（N）和第一掺杂的半导体层（2,3） 水平; 具有第二导电类型（P）并在半导体层（2,3）中延伸的第一体区（32）和第二体区（34）; 在所述第一和第二体区域（32,32）之间具有第一类型的导电性和比第一掺杂级别高的第二掺杂的富集区域（12），其在面向第一侧面（3a）的半导体层中延伸， 电介质填充区域（20），其在所述半导体层中延伸，面向所述第一侧面（3a），并且被所述富集区域（12）完全包围;以及栅极结构（29），其在第一 在富集区域（12）上的介电填充区域（20）上，第一体区域（32）的一部分上以及第二体区域（34）的一部分上的侧面（3a）。

公开(公告)号：WO2013128348A2

公开(公告)日：2013-09-06

申请号：PCT/IB2013/051422

申请日：2013-02-21

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto

CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/481 ,  H01L23/66 ,  H01L24/24 ,  H01L25/03 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/73259 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1011 ,  H01L2225/1047 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A base (2) carries a first chip (3) and a second chip (4) oriented differently with respect to the base and packaged in a package (6). Each chip integrates an antenna and a magnetic via (13). A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips (3, 4) even if the magnetic path is interrupted, and is formed by a first stretch (5c) coupled between the first magnetic-coupling element (13) of the first chip and the first magnetic-coupling element (12) of the second chip, and a second stretch (5f) coupled between the second magnetic-coupling element (12) of the first chip and the second magnetic-coupling element (13) of the second chip. The first stretch has a parallel portion (5c1, 5c3) extending parallel to the faces (2a, 2b) of the base. The first and second stretches have respective transverse portions (5i1, 5i2) extending on the main surfaces of the second chip, transverse to the parallel portion.

Abstract translation: 基座（2）承载相对于基座不同定向并封装在封装（6）中的第一芯片（3）和第二芯片（4）。 每个芯片集成天线和磁通（13）。 磁耦合路径连接芯片，形成磁路，即使磁路被中断也能够在芯片（3,4）之间传递信号和电力，并且通过耦合在第一磁性体之间的第一拉伸（5c）形成 第一芯片的耦合元件（13）和第二芯片的第一磁耦合元件（12）以及耦合在第一芯片的第二磁耦合元件（12）和第二芯片之间的第二拉伸（5f） 第二芯片的磁耦合元件（13）。 第一拉伸具有平行于基部的表面（2a，2b）延伸的平行部分（5c1,5c3）。 第一和第二延伸部具有横向于平行部分的在第二芯片的主表面上延伸的相应横向部分（5i1,5i2）。