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公开(公告)号：KR1019950005141B1
公开(公告)日：1995-05-18
申请号：KR1019910024066
申请日：1991-12-23
IPC: H04L7/00
Abstract: The circuit provides a dual mode clock supply device for network synchronization device of digital switching device (TDX-10). The circuit comprises a clock status detection module (101), a power reset module (103) to generate a reset signal in the case of power-on, a module (102) to recognize a power-on order, a master/slave signal generation module (104) to generate a master/slave control signal according to output signal from (101), a clock division module (106), an input synchronization signal control module (107), and a synchronization signal generation module(108).
Abstract translation: 该电路为数字开关装置（TDX-10）的网络同步装置提供双模时钟供电装置。 该电路包括时钟状态检测模块（101），用于在通电的情况下产生复位信号的功率复位模块（103），用于识别通电顺序的模块（102），主/从信号 生成模块（104），用于根据来自（101）的输出信号，时钟分割模块（106），输入同步信号控制模块（107）和同步信号生成模块（108）来产生主/从控制信号。
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Patent Agency Ranking
公开(公告)号：KR1019940007555B1
公开(公告)日：1994-08-19
申请号：KR1019910022460
申请日：1991-12-07
IPC: H04Q11/04
Abstract: The method interfaces a master clock generation processor of a digital processing phase locked loop and a peripheral processor in low class processor board through a telephone device bus. The method includes the steps of: (A) checking that a peripheral processor (PP) is in normal mode when a data is transmitted from a master clock generation processor (MGCP); (B) reading a first byte of a transmission buffer and transmitting data when the first byte of a buffer is H'oo; (C) checking the first byte of a buffer after a certain number of tries when the first byte of a buffer is not H'oo; and (D) recording the abnormal state of a PP and terminating the transmission.
Abstract translation: 该方法通过电话设备总线将数字处理锁相环的主时钟生成处理器和低级处理器板中的外围处理器连接。 该方法包括以下步骤：（A）当从主时钟生成处理器（MGCP）发送数据时，（A）检查外围处理器（PP）处于正常模式; （B）当缓冲器的第一个字节为H'oo时读取发送缓冲区的第一个字节并发送数据; （C）当缓冲器的第一个字节不是H'oo时，在一定次数的尝试之后检查缓冲区的第一个字节; 和（D）记录PP的异常状态并终止传输。
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公开(公告)号：KR1019930015436A
公开(公告)日：1993-07-24
申请号：KR1019910024066
申请日：1991-12-23
IPC: H04L7/00
Abstract: 본 발명은 전자교환기의 망동기 장치에 있어서, 이중화 동기회로에 관한 것으로, 특히 마스터/슬레이브(Master/Slave) 방식의 이중화 동기회로에 관한 것이다.
따라서, 본 발명은 이중화된 클럭공급장치에 마스터/슬레이브 방식을 하드웨어적으로 구형하므로써 이중화된 클럭 공급장치의 상태 저하 유발을 방지하고 유지보수시 시스템에 미치는 영향을 최소화하기 위한 것이다.-
公开(公告)号：KR1019930002066B1
公开(公告)日：1993-03-22
申请号：KR1019890020673
申请日：1989-12-30
IPC: H04L7/00
Abstract: The circuit processes the data transmitted between networks without loss by supplying clock locked to both the clock of an oscillator and the reference clock. It includes a processor interfacing circuit (1) for processing oscillation control signal and data from a processor, a control signal generator (2) for generating buffer enable signal and latch enable signal, a latch circuit (4), a OVCXO (7) for controlling the frequency of the output clock, and a buffer circuit (3) for buffering the oscillator control signal and data.
Abstract translation: 电路通过提供锁定在振荡器的时钟和参考时钟的时钟来处理在网络之间传输的数据而不损失。 它包括用于处理来自处理器的振荡控制信号和数据的处理器接口电路（1），用于产生缓冲器使能信号和锁存使能信号的控制信号发生器（2），一个锁存电路（4），一个OVCXO（7） 控制输出时钟的频率，以及用于缓冲振荡器控制信号和数据的缓冲电路（3）。
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