公开(公告)号：US10303620B2

公开(公告)日：2019-05-28

申请号：US16005385

申请日：2018-06-11

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/1036 ,  G06F9/48 ,  G06F12/1027 ,  G06F9/455 ,  G06F12/02 ,  G06F12/1045 ,  G06F12/12 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/109 ,  G06F12/123

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

公开(公告)号：US20190065226A1

公开(公告)日：2019-02-28

申请号：US15684002

申请日：2017-08-23

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Deepak K. Gupta ,  Ravi L. Sahita ,  Barry E. Huntley ,  Vedvyas Shanbhogue ,  Joseph F. Cihula

IPC: G06F9/455 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F9/45558 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2009/45583

Abstract: A processor comprises a register to store a first reference to a context data structure specifying a virtual machine context, the context data structure comprising a second reference to a target array and an execution unit comprising a logic circuit to execute a virtual machine (VM) based on the virtual machine context, wherein the VM comprises a guest operating system (OS) associated with a page table comprising a first memory address mapping between a guest virtual address (GVA) space and a guest physical address (GPA) space, receive a request by the guest OS to switch from the first memory address mapping to a second memory address mapping, the request comprising an index value and a first root value, retrieve an entry, identified by the index value, from the target array, the entry comprising a second root value, and responsive to determining that the first root value matches the second root value, cause a switch from the first memory address mapping to the second memory address mapping.

公开(公告)号：US20190018695A1

公开(公告)日：2019-01-17

申请号：US15978501

申请日：2018-05-14

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Dion Rodgers ,  Richard A. Uhlig ,  Lawrence O. Smith ,  Barry E. Huntley

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/38 ,  G06F9/54 ,  G06F13/24

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a hardware processor including event circuit to recognize a virtualization event, and evaluation circuit to determine whether to transfer control of the apparatus from a child guest to a parent guest in response to the virtualization event, wherein the child guest and the parent guest each include a bit per virtualization event to indicate whether the parent guest is to gain control when the virtualization event occurs.

公开(公告)号：US10114768B2

公开(公告)日：2018-10-30

申请号：US15249521

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Gur Hildesheim ,  Gilbert Neiger ,  Baiju V. Patel ,  Ron Rais

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/1027

Abstract: A processing system includes a processing core and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store a page table entry (PTE) comprising a mapping from a virtual memory page referenced by an application running on the processing core to an identifier of a memory frame of a memory, a first plurality of access permission flags associated with accessing the memory frame under a first privilege mode, and a second plurality of access permission flags associated with accessing the memory under a second privilege mode.

公开(公告)号：US09921984B2

公开(公告)日：2018-03-20

申请号：US14581677

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh M. Sankaran

IPC: G06F13/34

CPC classification number: G06F13/34

Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

公开(公告)号：US09858167B2

公开(公告)日：2018-01-02

申请号：US14973238

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Andrew V. Anderson ,  Richard A. Uhlig ,  David M. Durham ,  Ronak Singhal ,  Xiangbin Wu ,  Sailesh Kottapalli

IPC: G06F11/00 ,  G06F11/34 ,  G06F3/06 ,  G06F11/30 ,  G06F13/24

CPC classification number: G06F11/3466 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G06F11/3024 ,  G06F13/24

Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.

公开(公告)号：US20170337145A1

公开(公告)日：2017-11-23

申请号：US15612845

申请日：2017-06-02

Applicant: INTEL CORPORATION

Inventor： Carlos V. Rozas ,  Ilya Alexandrovich ,  Gilbert Neiger ,  Francis X. McKeen ,  Ittai Anati ,  Vedvyas Shanbhogue ,  Shay Gueron

IPC: G06F13/24 ,  G06F12/0806 ,  G06F21/00 ,  G06F21/85 ,  G06F12/08 ,  G06F21/71 ,  G06F12/0875

CPC classification number: G06F13/24 ,  G06F12/08 ,  G06F12/0806 ,  G06F12/0875 ,  G06F21/00 ,  G06F21/71 ,  G06F21/85 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/62

Abstract: Instructions and logic interrupt and resume paging in secure enclaves. Embodiments include instructions, specify page addresses allocated to a secure enclave, the instructions are decoded for execution by a processor. The processor includes an enclave page cache to store secure data in a first cache line and in a last cache line for a page corresponding to the page address. A page state is read from the first or last cache line for the page when an entry in an enclave page cache mapping for the page indicates only a partial page is stored in the enclave page cache. The entry for a partial page may be set, and a new page state may be recorded in the first cache line when writing-back, or in the last cache line when loading the page when the instruction's execution is being interrupted. Thus the writing-back, or loading can be resumed.

公开(公告)号：US09792222B2

公开(公告)日：2017-10-17

申请号：US14317571

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Ravi L. Sahita ,  Gilbert Neiger ,  David M. Durham ,  Vedvyas Shanbhogue ,  Michael Lemay ,  Ido Ouziel ,  Stanislav Shwartsman ,  Barry Huntley ,  Andrew V. Anderson

IPC: G06F12/10 ,  G06F12/14 ,  G06F9/455 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/145 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/651 ,  G06F2212/657 ,  Y02D10/13

Abstract: Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application associated with a first privilege level and a second application associated with a second privilege level, wherein a first set of privileges associated with the first privilege level includes a second set of privileges associated with the second privilege level; and an address validation component to validate, in view of an address translation data structure maintained by the first application, a mapping of a first address defined in a first address space of the second application to a second address defined in a second address space of the second application.

公开(公告)号：US20170206177A1

公开(公告)日：2017-07-20

申请号：US14997478

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Jr-Shian Tsai ,  Ravi L. Sahita ,  Mesut A. Ergin ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Jun Nakajima ,  Edwin Verplanke ,  Barry E. Huntley ,  Tsung-Yuan C. Tai

IPC: G06F13/24 ,  G06F9/455

CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F2009/45575 ,  G06F2009/45579

Abstract: Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.

公开(公告)号：US09703733B2

公开(公告)日：2017-07-11

申请号：US14318508

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Carlos V. Rozas ,  Ilya Alexandrovich ,  Gilbert Neiger ,  Francis X. McKeen ,  Ittai Anati ,  Vedvyas Shanbhogue ,  Shay Gueron

IPC: G06F12/00 ,  G06F13/24 ,  G06F12/0806 ,  G06F12/08 ,  G06F12/0875 ,  G06F21/00 ,  G06F21/71 ,  G06F21/85

CPC classification number: G06F13/24 ,  G06F12/08 ,  G06F12/0806 ,  G06F12/0875 ,  G06F21/00 ,  G06F21/71 ,  G06F21/85 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/62

Abstract: Instructions and logic interrupt and resume paging in secure enclaves. Embodiments include instructions, specify page addresses allocated to a secure enclave, the instructions are decoded for execution by a processor. The processor includes an enclave page cache to store secure data in a first cache line and in a last cache line for a page corresponding to the page address. A page state is read from the first or last cache line for the page when an entry in an enclave page cache mapping for the page indicates only a partial page is stored in the enclave page cache. The entry for a partial page may be set, and a new page state may be recorded in the first cache line when writing-back, or in the last cache line when loading the page when the instruction's execution is being interrupted. Thus the writing-back, or loading can be resumed.