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公开(公告)号：US20180300074A1
公开(公告)日：2018-10-18
申请号：US15488723
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Kamal Sinha , Bhushan M. Borole , Altug Koker , Joydeep Ray , Wenyin Fu
Abstract: Power for on-die heavily used local memories in general purpose graphics processing unit (GPGPU) applications may be reduced by using low latency read and high latency write operations. Power consumption in read heavy graphic operations can be reduced using a small memory footprint design with possible reduction of hot spotting in some embodiments.
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162.发明申请公开(公告)号：US20180295367A1
公开(公告)日：2018-10-11
申请号：US15483757
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Atthar H. Mohammed , Abhishek R. Appu , Stanley J. Baran , Sang-Hee Lee , Jong Dae Oh , Hiu-Fai R. Chan , Joydeep Ray , Narayan Biswal , Richmond Hicks , Arthur J. Runyan , Nausheen Ansari
IPC: H04N19/142 , H04N19/174
CPC classification number: H04N19/142 , H04N5/147 , H04N19/174 , H04N19/87 , H04N19/895 , H04N21/440281 , H04N21/44209
Abstract: Systems, apparatuses and methods may include a source device that generates a scene change notification in response to a movement of a camera, modifies an encoding scheme associated with the video content captured by the camera in response to the scene change notification, identifies a full-frame difference threshold, wherein scene analysis information includes frame difference data, and compares the frame difference data to an intermediate threshold that is less than the full-frame difference threshold, wherein the scene change notification is generated when the frame difference data exceeds the intermediate threshold. A sink device may obtain transport quality data associated with video content, modify an output parameter of a display based on the transport quality data, determine a view perspective of a still image containing a plurality of image slices, retrieve only a subset of the plurality of image slices based on the view perspective and decode the retrieved subset.
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公开(公告)号：US20180293778A1
公开(公告)日：2018-10-11
申请号：US15482803
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Kiran C. Veernapu , Prasoonkumar Surti , Joydeep Ray , Altug Koker , Eric G. Liskay
Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.
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公开(公告)号：US20180293703A1
公开(公告)日：2018-10-11
申请号：US15483829
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Michael Apodaca , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Abhishek R. Appu
Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.
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公开(公告)号：US20180293693A1
公开(公告)日：2018-10-11
申请号：US15482810
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , James A. Valerio , David Puffer , Abhishek R. Appu , Stephen Junkins
CPC classification number: G06T1/20 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0888 , G06F2212/1024 , G06F2212/302 , G06F2212/621 , G06F2212/656 , G06F2212/657 , G06T1/60
Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
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Patent Agency Ranking
公开(公告)号：US20180293692A1
公开(公告)日：2018-10-11
申请号：US15482808
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06T1/20 , G06F9/3009 , G06F9/30185 , G06F9/3851 , G06F9/461 , G06F9/4843
Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
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公开(公告)号：US20180293102A1
公开(公告)日：2018-10-11
申请号：US15482801
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Joydeep Ray , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Rajkishore Barik , Eriko Nurvitadhi , Nicolas C. Galoppo Von Borries , Tsung-Han Lin , Sanjeev Jahagirdar , Vasanth Ranganathan
Abstract: A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.
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168.发明申请公开(公告)号：US20180288433A1
公开(公告)日：2018-10-04
申请号：US15495531
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Jong Dae Oh , Abhishek R. Appu , Stanley J. Baran , Sang-Hee Lee , Atthar H. Mohammed , Hiu-Fai R. Chan , Joydeep Ray
IPC: H04N19/553 , H04N7/01 , H04N19/156
Abstract: Systems and methods may provide for occlusion detection in frame rate conversion. Detecting the occlusion allows frame rate conversion to be more accurately performed. In some embodiments, one or more stereoscopic depth cameras may be used to determine the depth of a moving object to more accurately determine the occlusion. In some embodiments, the compression ratio may be adjusted to balance the frame rate and power to help ensure compliance with a power budget. In at least some embodiments, the motion of a camera may be passed from a 3D render pipe to an encoder to avoid motion calculation and thereby saving power.
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公开(公告)号：US20180288423A1
公开(公告)日：2018-10-04
申请号：US15476990
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , ElMoustapha Ould-Ahmed-Vall , James M. Holland
IPC: H04N19/167 , H04N19/186 , H04N19/597 , G06T9/00 , H04N19/436 , G06T11/60
CPC classification number: G06T11/60 , G06T9/00 , H04N19/124 , H04N19/167 , H04N19/17 , H04N19/436 , H04N19/503
Abstract: An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.
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170.发明申请公开(公告)号：US20180288356A1
公开(公告)日：2018-10-04
申请号：US15477014
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Joydeep Ray , Abhishek R. Appu , Stanley J. Baran , Sang-Hee Lee , Atthar H. Mohammed , Jong Dae Oh , Hiu-Fai R. Chan , Ximin Zhang
IPC: H04N5/52 , H04N13/00 , H04N5/232 , H04N5/235 , H04N19/124 , H04N19/154
Abstract: An embodiment may include a display processor, memory to store a 2D frame corresponding to a projection from a 360 video, and a quality selector to select a quality factor for a block of the 2D frame based on quality information from neighboring blocks of the 2D frame, including blocks which are neighboring only in the 360 video space. The system may also include a range adjuster to adjust a search range for the 2D frame based on a search area of the 2D frame, a viewport manager to determine if a request for a viewport of the 2D frame extends beyond a first edge of the 2D frame and to fill the requested viewport with wrap-around image information, and/or a motion estimator to estimate motion information based on both color information and depth information. Other embodiments are disclosed and claimed.
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