公开(公告)号：US20030067350A1

公开(公告)日：2003-04-10

申请号：US10264942

申请日：2002-10-04

Applicant: STMicroelectronics S.A.

Inventor： Frederic Goutti ,  Christophe Forel

IPC: H03F001/14

CPC classification number: H03F1/305

Abstract: An amplifying circuit receiving an input voltage and a reference voltage equal to a fraction of the circuit supply voltage, the reference voltage provided by a time constant circuit, including a circuit for, upon power-on, inhibiting the amplifying circuit for as long as the difference between the value of the provided reference voltage and the voltage at the output of the time constant circuit is greater than a determined threshold.

Abstract translation: 接收输入电压和等于电路电源电压的一部分的参考电压的放大电路，由时间常数电路提供的参考电压，包括用于在上电时抑制放大电路的电路，只要 所提供的参考电压的值与时间常数电路的输出端的电压之差大于确定的阈值。

公开(公告)号：US20030053349A1

公开(公告)日：2003-03-20

申请号：US10233052

申请日：2002-08-30

Applicant: STMicroelectronics S.A.

Inventor： Sigrid Thomas

IPC: G11C007/00

CPC classification number: G11C17/18

Abstract: A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that connects the memory cells of a column. Each memory cell is also linked to a word line and to a third line. A gate of the transistor of a memory cell is linked to the word line, with each word line being linked to the gates of the transistors in a respective column. A third line is linked to the sources of the transistors of a row of memory cells. A bit line is linked to the capacitors of the transistors of a column. The voltage between the gate and the source of a transistor can thus be controlled via the word column and the third line.

Abstract translation: 存储器件包括以矩阵形式排列的多个存储单元。 每个存储单元包括串联连接的晶体管和电容器。 每个存储单元链接到连接列的存储单元的位线。 每个存储单元也链接到字线和第三行。 存储器单元的晶体管的栅极连接到字线，每个字线被连接到相应列中的晶体管的栅极。 第三条线连接到一行存储器单元的晶体管的源极。 位线连接到列的晶体管的电容器。 因此，可以通过字列和第三行来控制晶体管的栅极和源极之间的电压。

公开(公告)号：US20030046635A1

公开(公告)日：2003-03-06

申请号：US10115577

申请日：2002-04-02

Applicant: STMicroelectronics S.A.

Inventor： Laurent Murillo ,  Francois Ricodeau

IPC: H03M013/00

CPC classification number: H03M13/19

Abstract: A method for determining r error detection bits that can be associated with a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix of dimension rnullm. The parity control matrix is such that each column of matrix includes an odd number of null1snull greater than or equal to three. The present invention also relates to a method for determining a syndrome.

Abstract translation: 一种用于确定可以与要编码的m位的字相关联的r个错误检测位的方法，包括以下步骤：计算具有表示要编码的m位的字的m个分量的矢量的乘积和奇偶校验控制 维数rxm矩阵。 奇偶校验控制矩阵使得每列矩阵包括大于或等于三的奇数“1”。 本发明还涉及一种确定综合征的方法。

公开(公告)号：US20030034821A1

公开(公告)日：2003-02-20

申请号：US09955926

申请日：2001-09-18

Applicant: STMicroelectronics S.A.

Inventor： Catherine Mallardeau ,  Pascale Mazoyer ,  Marc Piazza

IPC: G06F001/04

CPC classification number: H01L27/10852 ,  H01L27/10882 ,  H01L27/10888

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

Abstract translation: 提供了一种集成电路，其具有包括局部掺杂的单晶衬底中形成的结的活性组分和位于活性组分之上的至少一个无源组分。 集成电路包括分离有源部件的第一绝缘层和无源部件的放宽，以及用于将无源部件与至少一个有源部件电连接的金属端子。 金属端子形成为第一绝缘层的厚度，并且具有从一个有源部件的接合极限突出的接触表面。 在优选实施例中，无源部件是电容器。 还提供了一种制造集成电路的方法，该集成电路包括MOS晶体管和矩阵中的DRAM单元的板载存储器平面。

公开(公告)号：US20030025189A1

公开(公告)日：2003-02-06

申请号：US10160277

申请日：2002-05-31

Applicant: STMICROELECTRONICS S.A.

Inventor： Jean-Luc Diot

IPC: H01L023/22

CPC classification number: H01L23/49548 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is provided that includes a flat leadframe having front and rear faces. The leadframe includes a central platform and elongate electrical connection leads distributed around this platform. Electrical connection wires connect the chip to the front face of the leads, and encapsulation means encapsulates the chip such that the rear face of the leadframe is visible. The electrical connection leads include an inner end part and an outer end part, the rear faces of the inner and outer end parts lie in the plane of the rear face of the leadframe, and the inner and outer end parts are connected by a branch whose rear face is set back with respect to the plane of the rear face of the leadframe so as to define a rear recess. The electrical connection wires are connected to the leads on the front face of their inner end part.

Abstract translation: 提供一种半导体封装，其包括具有前表面和后表面的扁平引线框架。 引线框架包括分布在该平台周围的中心平台和细长的电连接引线。 电连接线将芯片连接到引线的正面，并且封装装置封装芯片，使得引线框架的后表面可见。 电连接引线包括内端部和外端部，内端部和外端部的后表面位于引线框架的后表面的平面中，并且内端部和外端部通过分支连接， 背面相对于引线框架的后表面的平面设置，以便限定后凹部。 电连接线连接到其内端部前表面上的引线。

公开(公告)号：US20030008486A1

公开(公告)日：2003-01-09

申请号：US10184036

申请日：2002-06-27

Applicant: STMicroelectronics S.A.

Inventor： Thierry Schwartzmann ,  Herve Jaouen

IPC: H01L021/28

CPC classification number: H01L29/66659 ,  H01L29/7835

Abstract: A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.

Abstract translation: 具有漏极延伸的MOS晶体管包括在半导体衬底的上表面上的隔离块。 隔离块具有靠近晶体管的栅极的第一侧壁和基本上平行于第一侧壁的第二侧壁。 隔离块还包括在隔离块下方的衬底中的漏极延伸区域和与漏极延伸区域接触的漏极区域。 漏极区在衬底中，但不被隔离块覆盖。

公开(公告)号：US20030001659A1

公开(公告)日：2003-01-02

申请号：US10164840

申请日：2002-06-06

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G05F001/10

CPC classification number: G05F3/205 ,  G05F3/262

Abstract: A bias circuit integrated on a silicon wafer includes first, second and third branches. The first branch includes a first PMOS transistor in series with a first NMOS transistor. The second branch includes a second PMOS transistor, a second NMOS transistor and an electric resistor in series. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The first branch and the second branch are arranged as a current mirror. The third branch includes a third PMOS transistor in series with a third NMOS transistor. The third PMOS and NMOS transistors are arranged to maintain a drain voltage of the first PMOS transistor that is substantially identical to a drain voltage of the second PMOS transistor.

Abstract translation: 集成在硅晶片上的偏置电路包括第一，第二和第三分支。 第一分支包括与第一NMOS晶体管串联的第一PMOS晶体管。 第二分支包括第二PMOS晶体管，第二NMOS晶体管和串联的电阻器。 第一NMOS晶体管的栅极连接到第二NMOS晶体管的栅极。 第一分支和第二分支被布置为电流镜。 第三分支包括与第三NMOS晶体管串联的第三PMOS晶体管。 第三PMOS和NMOS晶体管布置成保持第一PMOS晶体管的漏极电压基本上等于第二PMOS晶体管的漏极电压。

公开(公告)号：US20030001594A1

公开(公告)日：2003-01-02

申请号：US10171086

申请日：2002-06-12

Applicant: STMicroelectronics S.A.

Inventor： Frederic Hasbani

IPC: G01R027/08

CPC classification number: G01R27/14 ,  G01R17/105 ,  G01R17/12

Abstract: A device for the comparison of two resistors is based upon analog information carried by currents. The device includes a measurement circuit for extracting the currents from the two resistors to be compared, and copies the currents to a parallel analog-digital converter that carries out the division of the extracted currents. The device converts the ratio of the extracted currents into a digital code that is the image of the ratio of the two resistors. The ratio is constantly re-updated as a function of environmental parameters of the circuit, such as the operating temperature. Also disclosed is a system for correcting the value of integrated compensated resistors. The system implements a device of this kind that does not use a reference voltage generator.

Abstract translation: 用于比较两个电阻的器件是基于电流携带的模拟信息。 该装置包括用于从要比较的两个电阻器中提取电流的测量电路，并将电流复制到并行模数转换器，其执行提取的电流的划分。 该装置将提取的电流的比率转换为作为两个电阻器的比率的图像的数字码。 该比率作为电路的环境参数（诸如操作温度）的函数不断地被更新。 还公开了用于校正积分补偿电阻器的值的系统。 该系统实现这种不使用参考电压发生器的装置。

公开(公告)号：US20030001228A1

公开(公告)日：2003-01-02

申请号：US10165051

申请日：2002-06-07

Applicant: STMicroelectronics S.A.

Inventor： Philippe Boivin ,  Francesco La Rosa

IPC: H01L029/00

CPC classification number: H01L27/0255 ,  H01L27/0251

Abstract: An integrated circuit on a silicon substrate includes at least one polysilicon line and at least one antistatic contact connecting the polysilicon line to the silicon substrate. The antistatic contact includes a thin oxide layer between the polysilicon line and the silicon substrate. The thin oxide layer is of a sufficiently small thickness so that a current flows across it by the tunnel effect when the polysilicon line is brought, relatively to the substrate, to a voltage greater or less than determined thresholds.

Abstract translation: 硅衬底上的集成电路包括至少一个多晶硅线和将多晶硅线连接到硅衬底的至少一个抗静电接触。 抗静电接触包括在多晶硅线和硅衬底之间的薄氧化层。 薄氧化物层具有足够小的厚度，使得当多晶硅线相对于衬底被带到大于或小于确定的阈值的电压时，电流通过隧道效应流过它。

公开(公告)号：US20020191432A1

公开(公告)日：2002-12-19

申请号：US10172179

申请日：2002-06-14

Applicant: STMicroelectronics S.A.

Inventor： Sigrid Thomas

IPC: G11C005/06

CPC classification number: H01L27/11233 ,  G11C17/12 ,  H01L27/112

Abstract: A read-only memory formed of cells, each of which includes, between a selection line and a bit line, the series connection of a memory element and of a selection MOS transistor with a gate connected to a read control line. The memory elements of blank cells are P-channel MOS transistors and the memory elements of programmed cells are uniformly N-type doped semiconductor regions.

Abstract translation: 由单元形成的只读存储器，每个单元在选择线和位线之间包括存储元件和选择MOS晶体管的串联连接，栅极连接到读控制线。 空白单元的存储元件是P沟道MOS晶体管，并且编程单元的存储元件是均匀的N型掺杂半导体区域。