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公开(公告)号：KR1019920005597B1
公开(公告)日：1992-07-09
申请号：KR1019890013187
申请日：1989-09-12
IPC: G06F1/00
Abstract: The circuit includes a manually operating means (3) for operating the circuit by manually manipulating switches. A preset signal generating means (5) generates pre-set signals at the instant when the manually operating means (3) is set, and a processor interface means (9) receives clock control data from a processor. A counter means (7) receives signals from the preset signal generating means and from the processor interface means to pre-set them by using the clock control data of the processor as the initial value. Upper and lower switches (1)(2) generate signals to increment or decrement the clock control data of the counter means, and a latching means (8) latches the clock control data of the counter means.
Abstract translation: 电路包括用于通过手动操作开关来操作电路的手动操作装置（3）。 预置信号发生装置（5）在手动操作装置（3）被设置的时刻产生预置信号，并且处理器接口装置（9）从处理器接收时钟控制数据。 计数器装置（7）从预设信号产生装置接收信号，并从处理器接口装置接收信号，以使用处理器的时钟控制数据作为初始值进行预设。 上下开关（1）（2）产生信号以递增或递减计数装置的时钟控制数据，锁存装置（8）锁存计数装置的时钟控制数据。
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Patent Agency Ranking
公开(公告)号：KR1019920004921B1
公开(公告)日：1992-06-22
申请号：KR1019890013188
申请日：1989-09-12
IPC: H03K19/00
Abstract: The circuit includes a TMR (triple modular redundancy) circuit (1) for receiving synchronizing clock codes to output selection information for normally operating synchronizing clocks. A clock receiving circuit (2) receives triplexed synchronizing clocks from a synchronizing clock generating section. A monitor circuit (3) monitors the state of the triplexed synchronizing clocks to output an information on it. A PROM (4) outputs code values for the synchronizing clocks, and a multiplexer (5) receives the triplexed synchronizing signals, and outputs the signals selected by the output values of the PROM (4). With the circuit, no separate clock selecting data is required.
Abstract translation: 该电路包括用于接收同步时钟代码以输出用于正常操作的同步时钟的选择信息的TMR（三模块冗余）电路（1）。 时钟接收电路（2）从同步时钟产生部分接收三重同步时钟。 监视器电路（3）监视三相同步时钟的状态以输出关于它的信息。 PROM（4）输出同步时钟的代码值，多路复用器（5）接收三路同步信号，并输出由PROM（4）的输出值选择的信号。 使用该电路，不需要单独的时钟选择数据。
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公开(公告)号：KR1019920003884B1
公开(公告)日：1992-05-16
申请号：KR1019890012896
申请日：1989-09-06
IPC: H03K19/00
Abstract: The triple modular redundancy (TMR) logic circuit selects selection signal (S) and TMR fault detection signal from master clock code (MCC) and transmits to a master clock selecting circuit and a TMR fault LED driver. The TMR logic circuit includes a first to a third latchs (1,5,9) for latching the data of the MCC, a first to a third multiplexer (2,6,10) for selecting and transmitting the MCC, a first to a third adder (3,7,11) connected to the first to the third multiplexer (2,6,10) respectively for executing add operation and for transmitting carries, and a fourth adder (12) for adding the carries transmitted from the first to the third adder (3,7,11).
Abstract translation: 三模块冗余（TMR）逻辑电路从主时钟码（MCC）选择选择信号（S）和TMR故障检测信号，并发送到主时钟选择电路和TMR故障LED驱动器。 TMR逻辑电路包括用于锁存MCC数据的第一至第三锁存器（1,5,9），用于选择和发送MCC的第一至第三复用器（2,6,10），第一到第三锁存器 分别连接到第一至第三多路复用器（2,6,10）的第三加法器（3,7,11），用于执行加法运算和发送运算;以及第四加法器（12），用于将从第一加到第三加法器 第三加法器（3,7,11）。
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公开(公告)号：KR1019920003362B1
公开(公告)日：1992-04-30
申请号：KR1019890012900
申请日：1989-09-06
IPC: H04L7/00
Abstract: A checking finds whether the current PLL (phase locked loop) is a master PLL or a slave PLL, and a proper action is taken depending on the checked result. If the phase difference of the PLL is not maintained at zero for a certain minimum period, the function for it is instantly stopped. During the occurrence of phase difference, the function is not carried out, but accumulates the input signals, and then, terminates the operation. If the phase difference data of the slave PLL is kept stable at zero for a certain period of time, an adjustment is carried out. When the output data level is shifted from "H" to "L", the phase is slowed down, but, when the data level is shifted from "L" to "H", an opposite action is carried out.
Abstract translation: 检查发现当前PLL（锁相环）是主PLL还是从PLL，并根据检查结果采取适当的动作。 如果PLL的相位差在一定的最小时间内没有保持为零，则其功能立即停止。 在发生相位差时，不执行该功能，而是累积输入信号，然后终止动作。 如果从PLL的相位差数据在一定时间段内保持为零，则进行调整。 当输出数据电平从“H”移位到“L”时，相位减慢，但是当数据电平从“L”移位到“H”时，执行相反的动作。
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