公开(公告)号：DE68923403D1

公开(公告)日：1995-08-17

申请号：DE68923403

申请日：1989-03-03

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10 ,  G11C7/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：DE68923402D1

公开(公告)日：1995-08-17

申请号：DE68923402

申请日：1989-03-03

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：DE68922784D1

公开(公告)日：1995-06-29

申请号：DE68922784

申请日：1989-03-03

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

公开(公告)号：IN174607B

公开(公告)日：1995-01-21

申请号：IN442DE1989

申请日：1989-05-19

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  BEGUN RALPH MURRAY

IPC: G06F15/00

公开(公告)号：NO176038C

公开(公告)日：1995-01-18

申请号：NO891585

申请日：1989-04-18

Applicant: IBM

Inventor： MILLING PHILIP ERNA ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

公开(公告)号：NO176038B

公开(公告)日：1994-10-10

申请号：NO891585

申请日：1989-04-18

Applicant: IBM

Inventor： MILLING PHILIP ERNA ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

公开(公告)号：HUT57923A

公开(公告)日：1991-12-30

申请号：HU389190

申请日：1990-06-18

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/362 ,  G06F15/82 ,  G06F13/14 ,  G06F9/00

Abstract: A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

公开(公告)号：CS9003042A2

公开(公告)日：1991-11-12

申请号：CS304290

申请日：1990-06-19

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/362 ,  G06F9/00 ,  G06F9/30

CPC classification number: G06F13/285 ,  G06F13/362

公开(公告)号：IT1230208B

公开(公告)日：1991-10-18

申请号：IT2064989

申请日：1989-05-25

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：IT1230191B

公开(公告)日：1991-10-18

申请号：IT2062689

申请日：1989-05-24

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  MILLING PHILLIP ERNA

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362 ,  G06F

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.