公开(公告)号：US20210120708A1

公开(公告)日：2021-04-22

申请号：US16659459

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Feras Eid

IPC: H05K9/00 ,  H01L23/60 ,  H01L21/48 ,  C08G61/12 ,  C08G73/06 ,  C08G85/00

Abstract: Embodiments may relate to a material to provide electrostatic discharge (ESD) protection in an electrical device. The material may include first and second electrically-conductive carbon allotropes. The material may further include an electrically-conductive polymer that is chemically bonded to the first and second electrically-conductive carbon allotropes such that an electrical signal may pass between the first and second electrically-conductive carbon allotropes. Other embodiments may be described or claimed.

公开(公告)号：US20210082822A1

公开(公告)日：2021-03-18

申请号：US16573943

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong ,  Johanna Swan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: An electronic interposer may be formed comprising an upper section, a lower section and a middle section. The upper section and the lower section may each have between two and four layers, wherein each layer comprises an organic material layer and at least one conductive route comprising at least one conductive trace and at least one conductive via. The middle section may be formed between the upper section and the lower section, wherein the middle section comprises up to eight layers, wherein each layer comprises an organic material and at least one conductive route comprising at least one conductive trace and at least one conductive via, and wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and thinner than a thickness of any of the layers of the lower section.

公开(公告)号：US20210066232A1

公开(公告)日：2021-03-04

申请号：US17098754

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Sri Ranga Sai Boyapati ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Javier Soto Gonzalez ,  Kwangmo Chris Lim ,  Aleksandar Aleksov

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/13 ,  H01L21/48

Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

公开(公告)号：US10937594B2

公开(公告)日：2021-03-02

申请号：US16606130

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Thomas L. Sounart ,  Aleksandar Aleksov ,  Feras Eid ,  Georgios C. Dogiamis ,  Johanna M. Swan ,  Kristof Darmawikarta

IPC: H01G4/14 ,  H05K1/02 ,  H05K1/03

Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a capacitor formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers. The capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes.

公开(公告)号：US20210043541A1

公开(公告)日：2021-02-11

申请号：US16532956

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/38 ,  H01L23/498 ,  H01L27/20 ,  H01L25/18 ,  H01L23/00 ,  H01L41/053 ,  H03H9/205 ,  H01L23/14 ,  H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L35/32 ,  H01L23/427 ,  H03H9/05 ,  H03H9/02

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

公开(公告)号：US20210036685A1

公开(公告)日：2021-02-04

申请号：US16526672

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Feras Eid ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H03H9/205 ,  H03F3/24 ,  H03H9/25 ,  H01L41/053 ,  H03H9/64 ,  H03H9/54 ,  H01L25/10 ,  H01L23/10 ,  H01L23/552

Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM) that includes a first acoustic wave resonator (AWR) die coupled with a package substrate. The RF FEM may also include a second AWR die coupled with the first AWR die. The first AWR die may be between the package substrate and the second AWR die. Other embodiments may be described or claimed.

公开(公告)号：US20210036682A1

公开(公告)日：2021-02-04

申请号：US16526633

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H03H9/05 ,  H01L23/538 ,  H01L25/18 ,  H01L27/20 ,  H01L25/00 ,  H01L41/053 ,  H01L23/00 ,  H03H9/58 ,  H01L41/047

Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM) that includes an acoustic wave resonator (AWR) die. The RF FEM may further include an active die coupled with the package substrate of the RF FEM. When the active die is coupled with the package substrate, the AWR die may be between the active die and the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US10820437B2

公开(公告)日：2020-10-27

申请号：US16335050

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Son V. Nguyen ,  Rajat Goyal ,  David B. Lampner ,  Dilan Seneviratne ,  Albert S. Lopez ,  Joshua D. Heppner ,  Srinivas V. Pietambaram ,  Shawna M. Liff ,  Nadine L. Dabby

IPC: G06F17/30 ,  H05K5/06 ,  H05K5/00 ,  H05K5/02 ,  G06F1/18 ,  G06F1/16 ,  G04G17/04

Abstract: The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace.

公开(公告)号：US20200315052A1

公开(公告)日：2020-10-01

申请号：US16402055

申请日：2019-05-02

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Johanna M. Swan ,  Georgios Dogiamis ,  Henning Braunisch ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Richard Dischler

IPC: H05K7/14 ,  H01P3/16 ,  H05K1/02 ,  H01P5/12

Abstract: Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

公开(公告)号：US20200211985A1

公开(公告)日：2020-07-02

申请号：US16236435

申请日：2018-12-29

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Aleksandar Aleksov

IPC: H01L23/64 ,  H01L49/02 ,  H01L23/13 ,  H01L23/538 ,  H01L21/48

Abstract: An embedded magnetic inductor coil is at least partially exposed in a recess that seats an embedded multi-chip interconnect bridge die on the coil. The embedded multi-chip interconnect bridge die provides a communications bridge between a dominant semiconductive device and a first semiconductive device.