公开(公告)号：JPS61135229A

公开(公告)日：1986-06-23

申请号：JP27236685

申请日：1985-12-02

Applicant: Rca Corp

Inventor： DONARUDO HENRII UIRISU

IPC: H03M1/12 ,  H03M1/00 ,  H04N7/26

CPC classification number: H03M1/201 ,  H03M1/365 ,  H04N19/90

公开(公告)号：US20240235572A9

公开(公告)日：2024-07-11

申请号：US18490931

申请日：2023-10-20

Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

Inventor： Arindam SANYAL

IPC: H03M1/46 ,  H03M1/06 ,  H03M1/20

CPC classification number: H03M1/462 ,  H03M1/0668 ,  H03M1/201

Abstract: A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.

公开(公告)号：US20230198540A1

公开(公告)日：2023-06-22

申请号：US17555270

申请日：2021-12-17

Applicant: Lawrence Livermore National Security, LLC

Inventor： Brandon Walter Buckley ,  Ryan Douglas Muir

IPC: H03M1/20

CPC classification number: H03M1/201

Abstract: Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a time-varying dither signal, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein each waveform has a waveform duration, wherein an average of the time-varying dither signal over multiple waveform durations is substantially zero, and wherein the time-varying dither signal varies over each waveform duration, generating a timing alignment, combining each waveform with the corresponding portion of the time-varying dither signal over each waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal, wherein the timing alignment is used to align the multiple instances of the waveform in the analog output signal.

公开(公告)号：US20190123753A1

公开(公告)日：2019-04-25

申请号：US16164015

申请日：2018-10-18

Applicant: Infineon Technologies AG

Inventor： Dietmar Straeussnigg

IPC: H03M1/20 ,  H03M1/12 ,  H03M1/18

CPC classification number: H03M1/201 ,  H03M1/1245 ,  H03M1/18 ,  H03M3/33 ,  H03M3/468

Abstract: In accordance with an embodiment, a method includes adding a dither signal to a first signal to generate a second signal, subtracting the dither signal from the first signal or subtracting the first signal from the dither signal to generate a third signal, performing a first sigma delta conversion of the second signal to a digital fourth signal, performing a second signal delta conversion of the third signal to a digital fifth signal, combining the digital fourth signal and the digital fifth signal to form a digital sixth signal.

公开(公告)号：US20190103877A1

公开(公告)日：2019-04-04

申请号：US15722265

申请日：2017-10-02

Applicant: Raytheon Company

Inventor： Ian S. Robinson ,  Daniel Thompson ,  James Toplicar

IPC: H03M1/20 ,  H03M1/60 ,  H03M1/66 ,  G02B6/35

CPC classification number: H03M1/201 ,  G02B6/3588 ,  H03M1/0641 ,  H03M1/12 ,  H03M1/60 ,  H03M1/66

Abstract: A method and system for data conversion includes an analog noise generator to generate a random, non-deterministic, analog noise signal. An adder adds the analog noise signal to an analog RF signal to produce a dithered analog signal. A first quantizer converts the analog noise signal to digital to produce a digital noise signal. A second quantizer converts the dithered analog signal to a digital equivalent signal. A digital dither adjustment module removes amplitude measurements of the digital noise signal from the digital equivalent signal to obtain a linearized digital representation of the analog RF signal.

公开(公告)号：US09806552B2

公开(公告)日：2017-10-31

申请号：US15169981

申请日：2016-06-01

Applicant: Analog Devices Global

Inventor： Paraic Brannick ,  Colin G. Lyden ,  Damien J. McCartney ,  Gabriel Banarie

IPC: H03M1/60 ,  H02J7/00 ,  G04F10/00 ,  H03M1/20 ,  H03M1/50 ,  H02J7/34

CPC classification number: H02J7/007 ,  G04F10/005 ,  H02J7/345 ,  H03M1/201 ,  H03M1/50 ,  H03M1/52 ,  H03M1/60

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

公开(公告)号：US09722537B2

公开(公告)日：2017-08-01

申请号：US14831784

申请日：2015-08-20

Applicant: Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03B1/00 ,  H03K3/015 ,  H03L7/093 ,  H03B5/12 ,  G04F10/00 ,  H03L7/08 ,  H03M1/00 ,  H03M1/20 ,  H03L7/089 ,  H03L7/197 ,  H03K3/03

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

公开(公告)号：US09331709B2

公开(公告)日：2016-05-03

申请号：US14162572

申请日：2014-01-23

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/20 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/0668 ,  H03M1/462 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

公开(公告)号：US20160056799A1

公开(公告)日：2016-02-25

申请号：US14831119

申请日：2015-08-20

Applicant: Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03K3/015 ,  H03B1/00

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。

公开(公告)号：US09231611B2

公开(公告)日：2016-01-05

申请号：US14162567

申请日：2014-01-23

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Jesper Steensgaard-Madsen

IPC: H03M1/06 ,  H03M1/20 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/0668 ,  H03M1/462 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract translation: 一种模数转换器（ADC）系统和方法。 根据一个实施例的ADC系统包括被配置为对模拟信号值和模拟抖动值的组合进行采样的采样数模转换器，以及包括失配整形编码器的控制电路。 控制电路被配置为在模数转换操作期间将多个数字代码顺序地应用于采样数模转换器，以导出表示模拟信号值和模拟抖动值的组合的数字代码。 呈现了几个实施例。