公开(公告)号：US20020168028A1

公开(公告)日：2002-11-14

申请号：US10103575

申请日：2002-03-21

Applicant: STMICROELECTRONICS S.A.

Inventor： Marc Joisson ,  Luc Garcia ,  Marc Gens

IPC: H03K009/00

CPC classification number: H04L27/1566

Abstract: A receiver of a frequency-modulated signal is provided. The receiver includes a frequency-transposition unit for lowering the frequency of the frequency-modulated signal, and a digital demodulator for regenerating a digital signal from the frequency-transposed signal. The frequency-transposition unit includes a local oscillator for generating a local oscillator signal used in lowering the frequency of the frequency-modulated signal. The frequency-transposed signal is sampled in the digital demodulator at the rate of a sampling signal, and the sampling signal is generated by the local oscillator of the frequency-transposition unit. In a preferred embodiment, the local oscillator includes at least one frequency-divider circuit that delivers the sampling signal. Also provided is a method for regenerating a digital signal from a frequency-modulated signal.

Abstract translation: 提供了调频信号的接收机。 接收机包括用于降低频率调制信号的频率的频率转置单元和用于从频率转置信号再生数字信号的数字解调器。 频率转置单元包括本地振荡器，用于产生用于降低频率调制信号的频率的本地振荡器信号。 在数字解调器中以采样信号的速率采样频移信号，采样信号由频移单元的本地振荡器产生。 在优选实施例中，本地振荡器包括传送采样信号的至少一个分频器电路。 还提供了一种从频率调制信号再生数字信号的方法。

公开(公告)号：US20020167357A1

公开(公告)日：2002-11-14

申请号：US10144636

申请日：2002-05-13

Applicant: STMicroelectronics S.A.

Inventor： Claude Renous

IPC: H03F003/45

CPC classification number: H03F3/3023 ,  H03F1/086 ,  H03F3/3062 ,  H03F3/45659

Abstract: A differential amplifier may include a first stage including a first transistor and a second transistor having the same polarity and assembled to constitute a differential amplifier. The first stage may be supplied by first and second mirror current sources. The differential amplifier may further include a common mode control circuit, which may include two inputs receiving a reference voltage VCM and a common mode voltage controlling the first and second mirror current sources, respectively. The differential amplifier may further include a Miller gain stage having inputs and for a setting gain-band product. The differential amplifier may further include an unlocking circuit, inserted between the common mode voltage and the Miller gain stage inputs, to cause the Miller gain stage to conduct on circuit start-up.

Abstract translation: 差分放大器可以包括第一级，其包括具有相同极性的第一晶体管和第二晶体管，并组装以构成差分放大器。 第一级可以由第一和第二反射镜电流源提供。 差分放大器还可以包括共模控制电路，其可以包括接收参考电压VCM的两个输入端和分别控制第一和第二反射镜电流源的共模电压。 差分放大器还可以包括具有输入和设置增益带积的米勒增益级。 差分放大器还可以包括插入在共模电压和米勒增益级输入之间的解锁电路，以使得米勒增益级在电路启动时进行。

公开(公告)号：US20020163027A1

公开(公告)日：2002-11-07

申请号：US10114672

申请日：2002-04-02

Applicant: STMICROELECTRONICS S.A.

Inventor： Thomas Skotnicki ,  Emmanuel Josse

IPC: H01L027/108

CPC classification number: H01L29/66666 ,  H01L29/165 ,  H01L29/7827

Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.

Abstract translation: 垂直绝缘栅晶体管包括在半导体衬底上的垂直柱，其顶部包括源极和漏极区中的一个，位于柱的侧面和衬底顶表面上的栅极电介质层，以及半导体 门静置在栅介质层上。 源极和漏极区域中的另一个位于柱PIL的底部，并且绝缘栅极包括搁置在柱的侧面上的隔离的外部部分15和位于源极和漏极区域之间的柱内的隔离的内部部分14 。 隔离的内部部分通过在源极和漏极区域之间延伸的两个连接半导体区域PL1，PL2从隔离的外部部分侧向分离，并形成两个非常细的柱。

公开(公告)号：US20020156818A1

公开(公告)日：2002-10-24

申请号：US10068568

申请日：2002-02-06

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Nicolas Lafargue

IPC: G06F007/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F7/575 ,  G06F7/768 ,  G06F9/30025 ,  G06F9/30032

Abstract: A microprocessor comprises a central processing unit having an arithmetic and logic unit with two inputs and one input fed-back to one of the inputs through a data path. The arithmetic and logic unit performs arithmetic and logic operations on binary words temporarily stored within registers in the central processing unit. The central processing unit further includes a shift unit in the data path of the arithmetic and logic unit for performing operations to shift bits in the binary words applied thereto. A selection circuit selects a shift operation to be performed. An inverting circuit inverts the ordering of the bits in the binary words applied thereto, which are in the data path of the arithmetic and logic unit, and a selection circuit selects the inversion operation when the latter is required.

Abstract translation: 微处理器包括中央处理单元，其具有具有两个输入的算术和逻辑单元，以及通过数据路径反馈到其中一个输入的一个输入。 算术和逻辑单元对临时存储在中央处理单元中的寄存器内的二进制字执行算术和逻辑运算。 中央处理单元还包括在算术和逻辑单元的数据路径中的移位单元，用于执行将应用于其中的二进制字中的位移位的操作。 选择电路选择要执行的移位操作。 反相电路将应用于其中的二进制字中的位的顺序反转在算术和逻辑单元的数据路径中，并且当需要后者时，选择电路选择反转操作。

公开(公告)号：US20020121649A1

公开(公告)日：2002-09-05

申请号：US10068308

申请日：2002-02-05

Applicant: STMicroelectronics S.A.

Inventor： Didier Belot

IPC: H01L031/0328

CPC classification number: H01L27/0248 ,  H01L29/0603 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure of protection of an area of a semiconductor wafer including a lightly-doped substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer. The structure includes a very heavily-doped wall of the first conductivity type having substantially the depth of the upper portion. The wall is divided into segments, each of which is connected to a ground plane.

Abstract translation: 包括半导体晶片的区域的保护结构，该半导体晶片的区域包括第一导电类型的轻掺杂衬底，以抵抗可能从形成在晶片的第二区域的上部的部件注入的高频噪声。 该结构包括基本上具有上部深度的第一导电类型的非常重掺杂的壁。 墙被分成段，每个段连接到接地平面。

公开(公告)号：US20020109536A1

公开(公告)日：2002-08-15

申请号：US10021287

申请日：2001-10-30

Applicant: STMicroelectronics S.A.

Inventor： Bruno Gailhard ,  Olivier Ferrand

IPC: H03L007/06

CPC classification number: H03K3/03 ,  H03L7/0997

Abstract: A generator includes an oscillator for producing a clock signal from N logic signals representing an N-bit control number, with N being an integer greater than 1. The oscillator has Nnull1 components. The N most significant components are each assigned a place value i ranging from 1 to N, and a least significant component provides the clock signal. At least one component with a place value i greater than 1 includes first and second arms. The first arm includes a cell and a first switch connected in series, and the second arm includes 1null21 cells and a second switch connected in series. Each cell includes an odd number of inverters.

Abstract translation: 发生器包括用于从表示N位控制号的N个逻辑信号产生时钟信号的振荡器，其中N是大于1的整数。振荡器具有N + 1个分量。 N个最重要的组件每个被分配一个从1到N的位置值i，并且最不重要的组件提供时钟信号。 位置值i大于1的至少一个部件包括第一和第二臂。 第一臂包括串联连接的单元和第一开关，第二臂包括1 + 21单元和串联连接的第二开关。 每个单元包括奇数个逆变器。

公开(公告)号：US20020101916A1

公开(公告)日：2002-08-01

申请号：US10045956

申请日：2001-10-26

Applicant: STMicroelectronics S.A.

Inventor： Maurice Le Van Suu

IPC: H04L005/16

CPC classification number: H04L27/0008 ,  H04L27/0012

Abstract: A modulation/demodulation device capable of operating with several types of modulation using different carrier frequencies may include a modulator which modulates at least one signal by a signal of a predetermined duration and representative of a binary information supplied by a microprocessor. The device may also include a demodulator which demodulates the modulated signals arriving from a remote site. This may be done by determining the type of modulation of the received signals and their carrier frequency (or frequencies), supplying signals from an analysis of the signals received according to the determined type of modulation, and detecting the signals of determined duration representative of binary information to make them accessible to the microprocessor.

Abstract translation: 能够使用不同载波频率进行多种调制的调制/解调装置可以包括调制器，其通过预定持续时间的信号调制至少一个信号，并且代表由微处理器提供的二进制信息。 该设备还可以包括解调器，其解调从远程站点到达的调制信号。 这可以通过确定接收信号的调制类型及其载波频率（或频率）来​​完成，从根据所确定的调制类型接收的信号的分析提供信号，以及检测表示二进制的确定持续时间的信号 信息使微处理器可访问。

公开(公告)号：US20020095637A1

公开(公告)日：2002-07-18

申请号：US10097785

申请日：2002-03-14

Applicant: STMicroelectronics S.A.

Inventor： Jean-Marie Gaultier

IPC: H04L001/18 ,  G08C025/02

CPC classification number: H04L29/06 ,  H04L1/1803 ,  H04L69/324

Abstract: A method for communicating between a transmitting unit and a receiving unit. A messages formed by elementary messages is transmitted from the transmitting unit to the receiving unit, and at least one reception bit is transmitted from the receiving unit to the transmitting unit. The reception bit (or bits) allows the transmitting unit to determine the elementary message that is to be transmitted next. In a preferred method, at least two reception bits are transmitted from the receiving unit and the values of the reception bits indicate the elementary message that is to be transmitted next by the transmitting unit. The present invention also provides a receiving device for receiving messages from a transmitting device. The receiving device includes an interface for receiving a transmitted message from the transmitting device, means for analyzing a received elementary message to determine if it was properly received, and a transmitter for transmitting at least one reception bit to the transmitting device. The reception bit (or bits) indicates the elementary message that is to be transmitted next by the transmitting unit. In one preferred embodiment, the transmitter transmits at least two reception bits whose values indicate the elementary message that is to be transmitted next by the transmitting unit.

Abstract translation: 一种用于在发送单元和接收单元之间进行通信的方法。 由基本消息形成的消息从发送单元发送到接收单元，并且至少一个接收位从接收单元发送到发送单元。 接收位（或比特）允许发送单元确定接下来要发送的基本消息。 在优选方法中，从接收单元发送至少两个接收比特，并且接收比特的值表示发送单元将要发送的基本消息。 本发明还提供一种用于从发送装置接收消息的接收装置。 接收装置包括用于从发送装置接收发送的消息的接口，用于分析接收到的基本消息以确定其是否被正确接收的装置，以及用于向发送装置发送至少一个接收比特的发送机。 接收位（或位）表示发送单元接下来要发送的基本消息。 在一个优选实施例中，发射机发送至少两个接收位，其值表示发送单元将要发送的基本消息。

公开(公告)号：US20020090781A1

公开(公告)日：2002-07-11

申请号：US10042506

申请日：2002-01-08

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Catherine Mallardeau

IPC: H01L021/8242

CPC classification number: H01L27/1087 ,  H01L27/10832

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of Nnull doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

Abstract translation: 通过从硅衬底外延生长制造DRAM型电池的工艺包括生长硅锗层和硅层; 叠加第一层N +掺杂硅和第二层P掺杂硅; 以及在硅衬底上形成晶体管。 该方法还包括蚀刻晶体管的延伸中的沟槽，以提供在预定深度上相对于硅层访问硅锗层以形成横向空腔，以及在沟槽和侧向空腔中形成电容器 。

公开(公告)号：US20020050610A1

公开(公告)日：2002-05-02

申请号：US09921280

申请日：2001-08-02

Applicant: STMicroelectronics S.A.

Inventor： Cyrille Dray

IPC: H01L029/788

CPC classification number: H01L29/42324 ,  H01L29/7886

Abstract: A non-volatile memory cell includes a MOS transistor having a ring arrangement and comprising a floating gate, a center electrode at a center of the ring arrangement and surrounding the floating gate, and at least one peripheral electrode along a periphery of the ring arrangement.

Abstract translation: 非易失性存储单元包括具有环形布置并包括浮动栅极的MOS晶体管，环形布置的中心处的中心电极并且围绕浮置栅极，以及沿环形布置的周边的至少一个外围电极。