Abstract:
Methods, devices, and instructions for performing a reverse translation lookaside buffer (TLB) look-up using a physical address input, including obtaining with a first processor the physical address input, wherein the physical address input indicates a physical address corresponding to a shared memory, obtaining a first mask associated with a first virtual address from a first TLB entry within a TLB associated with the first processor, wherein the obtained first mask is a bit pattern, obtaining from the first TLB entry a first page frame number associated with the shared memory, applying the obtained first mask to the obtained first page frame number to generate a first value, applying the obtained first mask to the obtained physical address input to generate a second value, and comparing the first value and the second value to determine whether the first value and the second value match.
Abstract:
A solution is proposed for managing a database in a data-processing system. A corresponding method (600) comprises the steps of providing (606-675), for a set of virtual tables each one comprising a set of virtual columns each one of a data type, a polymorph table stored in the database and a mapping structure, the polymorph table comprising a discrimination column for storing an identifier of the virtual tables and a total number of polymorph columns of each data type equal to a maximum number of the virtual columns of the data type in the virtual tables, and the mapping structure storing mapping information mapping each virtual column to a corresponding one of the polymorph columns of the same data type, receiving (678) a virtual access request for accessing at least part of the virtual tables, the virtual access request being based on at least a selected one of the virtual columns of at least a selected one of the virtual tables, retrieving (681) selected mapping information mapping each selected virtual column to a selected one of the polymorph columns from the mapping structure, converting (684-687) the virtual access request into a polymorph access request for the polymorph table according to the identifier of said at least one selected virtual table and the selected mapping information, and accessing (690-699) the polymorph table according to the polymorph access request.
Abstract:
A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor.
Abstract:
Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.