Abstract:
적어도 2개의 실행 유닛이 2개의 컴포넌트로서 제공되며, 추가의 컴포넌트로서 전환 수단이 제공되며, 컴퓨터 시스템에서 적어도 2개의 작동 모드 간에 전환이 이루어지며, 제1 작동 모드는 비교 모드에 상응하고, 제2 작동 모드는 성능 모드에 상응하는 신호 생성 방법에 있어서, 컴퓨터 시스템의 컴포넌트에서 현재 존재하는 작동 모드를 나타내는 모드 신호가 생성되고 그리고/또는 그 모드 신호의 변경값이 생성되며, 적어도 모드 신호의 변경값 및/또는 모드 신호 자체는 컴포넌트 외부에서 활용되는 것을 특징으로 한다. 컴퓨터 시스템, 작동 모드, 비교 모드, 실행 모드, 전환 장치, 신호.
Abstract:
The invention relates to a method and device for switching over in a computer system having at least two execution units. According to the invention, switching occurs between at least two operating modes, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. The invention is characterized in that the execution units can be connected to an internal bus of the computer system. In the performance mode, at least two execution units are connected to the internal bus and when switching between the performance mode and the comparison mode, at least one execution unit is disconnected from the internal bus by a switch controlled by the changeover switch.
Abstract:
The invention relates to a method and a device for evaluating a signal of a computer system comprising at least two execution units. It is possible to switch between at least two operating modes in said computer system, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. The invention is characterised in that a mode signal indicating the current operating mode and/or changes in the mode signal can be generated in the computer system, and at least changes in the mode signal and/or the mode signal itself can be used for evaluation outside the computer system.
Abstract:
The invention relates to a method and a device for switching and data comparison in a computer system comprising at least two processing units which respectively process data at a pre-determined rate. Switching means are provided for switching between at least two operating modes, in addition to comparison means, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. The invention is characterised in that synchronisation means are provided, said synchronisation means associating rate information with the pre-determinable data according to a processing unit, and at least the comparison means take into account said rate information for the corresponding data.
Abstract:
The invention relates to a method and a device for switching between at least two operating modes (SM, LM) of a processor unit (100, 101) comprising at least two execution units (ALUA, ALUB) for running programs (P1, P2, P3). At least one characteristic (K2) associated with at least the programs (P1, P2, P3) differentiates between the at least two operating modes (SM, LM), and switching between the operating modes is carried out according to the characteristic (K1-K4, KB) such that the processor unit (100, 101) runs the programs (P1, P2, P3) according to the associated operating mode.
Abstract:
Eine Anordnung (10) zur redundanten Datenverarbeitung umfasst einen integrierten Schaltkreis (20), in dem die Funktionalität eines Mehrkernprozessors (30) implementiert ist. Prozessorkerne (40; 50) des Mehrkernprozessors sind jeweils ausgebildet, ein Nutzprogramm auszuführen, wobei Ergebnisse, die sich aus einer Ausführung des Nutzprogramms durch verschiedene der Prozessorkerne ergeben, mittels eines Vergleichsbausteins (60) der Anordnung verglichen werden können. Die Prozessorkerne unterscheiden sich untereinander hinsichtlich einer Adress- oder Datenstruktur (AS1, AS2; DS1, DS2), die seitens eines Prozessorkerns jeweils zum Abspeichern und Auslesen von Daten in oder aus einem dem jeweiligen Prozessorkern zugeordneten Speicherbereich (70; 80) verwendet wird. Die einzelnen Prozessorkerne sind in dem integrierten Schaltkreis hardwaremäßig zumindest teilweise separat implementiert.
Abstract:
A method includes, in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data. A redundant storage configuration is selected in the memory controller depending on the available memory space. Redundancy information is calculated over the data using the selected redundant storage configuration. The data and the redundancy information are written to the available memory space in the memory.
Abstract:
The present invention relates to a symmetric multi-core processor arrangement for a safety critical system, comprising: a symmetric multiprocessor (14; 30) having at least two cores (6-9; 39-46) and a memory (11; 48) shared for the at least two cores; and a hypervisor (13; 47) connected to the symmetric multi-processor, and configured to organize access to the at least two cores for at least a diagnostic application (12; 37, 38) checking the safety critical system; wherein, during use, the diagnostic application is configured to read from and write to the memory, and the hypervisor is configured to read only from the memory.
Abstract:
Die Erfindung betrifft ein Verfahren zur Fehlerüberwachung eines Rechnersystems mit mindestens zwei Recheneinheiten, wobei das Rechnersystem zwischen einem ersten und einem zweiten Betriebsmodus umgeschaltet wird und der erste Betriebsmodus einem Performanzmodus und der zweite Betriebsmodus einem Vergleichsmodus entspricht. Bei einem Verfahren, bei welchem das Rechnersystem mit mindestens zwei Recheneinheiten, das in unterschiedlichen Betriebsmodi arbeiten kann, regelmäßig einen sicheren Zustand einnimmt, überwacht ein Mustererkennungsalgorithmus die Betriebsmodi, wobei auf einen Fehler erkannt wird, wenn mindestens ein Betriebsmodus von dem Mustererkennungsalgorithmus abweicht.