公开(公告)号：EP0862333B1

公开(公告)日：2002-05-29

申请号：EP98105936.3

申请日：1992-10-31

Applicant: General Instrument Corporation

Inventor： Shen, Paul ,  Paik, Woo H. ,  Krause, Edward A.

IPC: H04N7/50 ,  H04N7/36

CPC classification number: G11C7/1075 ,  G11C7/1036 ,  H04N19/423 ,  H04N19/433 ,  H04N19/51 ,  H04N19/61

公开(公告)号：EP1054772A4

公开(公告)日：2001-09-26

申请号：EP99906895

申请日：1999-02-10

Applicant: LEXMARK INT INC

Inventor： GIBSON BRUCE DAVID ,  PARISH GEORGE KEITH

IPC: B41J2/01 ,  B41J2/045 ,  B41J2/05 ,  B41J2/055 ,  B41J2/125 ,  B41J2/175 ,  B41J25/34 ,  B41J29/38 ,  G11C7/10 ,  G11C8/10 ,  G11C16/02 ,  B41J1/00 ,  B41J29/393 ,  G11C8/00

CPC classification number: B41J2/17546 ,  B41J2/04541 ,  B41J2/04563 ,  B41J2/0458 ,  B41J2/17526 ,  B41J25/34 ,  B41J2202/17 ,  G11C7/1036 ,  G11C8/10

Abstract: An ink jet print head identification system for providing information to the electronics (98) of an ink jet printer includes a plurality of shift registers (92) having a plurality of address lines. The memory input of each shift register is electrically connected to a memory matrix that supplies digital bits of information to the shift registers (92) in response to receiving a decode input signal (94).

公开(公告)号：EP1078370A1

公开(公告)日：2001-02-28

申请号：EP99914242.5

申请日：1999-03-29

Applicant: ATMEL CORPORATION

Inventor： PATHAK, Saroj ,  ROSENDALE, Glen, A. ,  PAYNE, James, E. ,  HANGZO, Nianglamching

IPC: G11C7/00

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/1036

Abstract: A sense amplifier (200) for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controlled manner (270), in response to a control pulse (SAEN). The control pulse (SAEN) is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps (200) are utilized to read out in parallel fashion the N memory cells (bits) comprising an accessed memory location. The sense amps (200) are therefore active only of a period of time sufficient to read out a memory cell.

公开(公告)号：EP0862333A3

公开(公告)日：2000-09-27

申请号：EP98105936.3

申请日：1992-10-31

Applicant: General Instrument Corporation

Inventor： Shen, Paul ,  Paik, Woo H. ,  Krause, Edward A.

IPC: H04N7/50 ,  H04N7/36

CPC classification number: G11C7/1075 ,  G11C7/1036 ,  H04N19/423 ,  H04N19/433 ,  H04N19/51 ,  H04N19/61

Abstract: A multiple serial access memory is provided. A dynamic random access memory (30) is addressed to input data thereto and output data therefrom. Rows of data are output from the array (50) in response to address signals (34, 36, 38) provided thereto. A plurality of serial output ports (44, 46, 48) is coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports (44, 46, 48) are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register (62, 64, 66, ... 68) having a length equal to the width of the memory array (30). The shift register is responsive to a first timing signal (42, 52) for latching a row of data from the array (30). A second timing signal actuates the shift register to shift a row of latched data. A serial access selector (70) coupled to the shift register outputs a selected portion of the shifted data from the serial output port. The memory has particular application as the frame store for a motion compensated interframe image coding/decoding system.

公开(公告)号：EP0590953B1

公开(公告)日：1999-09-01

申请号：EP93307716.6

申请日：1993-09-29

Applicant: NEC CORPORATION

Inventor： Okimura, Yasunori, c/o NEC IC Microcomp. Syst. Ltd

IPC: G11C7/00

CPC classification number: G11C7/1036

公开(公告)号：EP0851424A2

公开(公告)日：1998-07-01

申请号：EP97310490.4

申请日：1997-12-23

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Ohta, Yoshiji

IPC: G11C7/00

CPC classification number: G11C7/1036 ,  G11C16/0491

Abstract: There is provided a serial access system semiconductor storage device capable of reducing access time and decreasing consumption current. A memory cell array 1 including a plurality of memory cells CELL0, CELL1, ... and shift registers 2A and 2B having a plurality of latch circuits SR0, SR2, ..., SR1, SR3, ... connected in series are provided. The shift registers 2A and 2B once hold data, received from the memory cell array 1 via a bit line in a read operation, in the latch circuits SR0, SR2, ..., SR1, SR3, ... and serially output the held data in the order in which the latch circuits are arranged. The latch circuits SR0, SR2, ..., SR1, SR3, ... sense-amplify the data stored in the memory cells inside the memory cell array 1.

Abstract translation: 提供了一种能够减少存取时间并降低消耗电流的串行存取系统半导体存储装置。 提供包括具有多个串联连接的锁存电路SR0，SR2，...，SR1，SR3，...的多个存储单元CELL0，CELL1，...的移位寄存器2A和2B的存储单元阵列1 。 移位寄存器2A和2B一旦在锁存电路SR0，SR2，...，SR1，SR3 ...中保持从存储单元阵列1经由读取操作中的位线接收到的数据，并且串行输出保持的 数据按照锁存电路的顺序排列。 锁存电路SR0，SR2，...，SR1，SR3，...对存储在存储单元阵列1内的存储单元中的数据进行感测放大。

公开(公告)号：EP0763827A3

公开(公告)日：1997-12-10

申请号：EP96112512.7

申请日：1996-08-02

Applicant: NEC CORPORATION

Inventor： Kobayashi, Shotaro, c/o NEC Corporation

IPC: G11C7/00

CPC classification number: G11C7/1036 ,  G11C7/1075

Abstract: A semiconductor memory is disclosed which has a serial access port transferring data consisting of a plurality of bits in a sequential manner. The serial access port includes a plurality of data registers provided correspondingly to a plurality of pairs of bit lines and divided into a plurality of groups, each of which is equal in number to the data to be transferred at one time, and a plurality of power control transistors each controls supply of a power to one of the registers of one group and to one of the registers of a different group. The registers in one group which is selected are thus supplied with a power from different power control transistors from each other.

公开(公告)号：EP0763827A2

公开(公告)日：1997-03-19

申请号：EP96112512.7

申请日：1996-08-02

Applicant: NEC CORPORATION

Inventor： Kobayashi, Shotaro, c/o NEC Corporation

IPC: G11C7/00

CPC classification number: G11C7/1036 ,  G11C7/1075

Abstract: A semiconductor memory is disclosed which has a serial access port transferring data consisting of a plurality of bits in a sequential manner. The serial access port includes a plurality of data registers provided correspondingly to a plurality of pairs of bit lines and divided into a plurality of groups, each of which is equal in number to the data to be transferred at one time, and a plurality of power control transistors each controls supply of a power to one of the registers of one group and to one of the registers of a different group. The registers in one group which is selected are thus supplied with a power from different power control transistors from each other.

Abstract translation: 公开了一种半导体存储器，其具有串行访问端口以顺序方式传送由多个位组成的数据。 串行访问端口包括对应于多对位线而设置的多个数据寄存器，并被分成多个组，每个组的数目与要一次传送的数据的数目相等，并且多个功率 控制晶体管每个都控制向一个组的一个寄存器和另一个组的寄存器之一提供电源。 因此被选择的一个组中的寄存器因此被从不同的功率控制晶体管彼此供电。

公开(公告)号：EP0543197A3

公开(公告)日：1994-04-20

申请号：EP92118660.7

申请日：1992-10-31

Applicant: GENERAL INSTRUMENT CORPORATION OF DELAWARE

Inventor： Shen, Paul ,  Paik, Woo H. ,  Krause, Edward A.

IPC: G11C7/00 ,  G11C11/409

CPC classification number: G11C7/1075 ,  G11C7/1036 ,  H04N19/423 ,  H04N19/433 ,  H04N19/51 ,  H04N19/61

Abstract: A multiple serial access memory is provided. A dynamic random access memory (30) is addressed to input data thereto and output data therefrom. Rows of data are output from the array (50) in response to address signals (34, 36, 38) provided thereto. A plurality of serial output ports (44, 46, 48) is coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports (44, 46, 48) are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register (62, 64, 66, ... 68) having a length equal to the width of the memory array (30). The shift register is responsive to a first timing signal (42, 52) for latching a row of data from the array (30). A second timing signal actuates the shift register to shift a row of latched data. A serial access selector (70) coupled to the shift register outputs a selected portion of the shifted data from the serial output port. The memory has particular application as the frame store for a motion compensated interframe image coding/decoding system.

Abstract translation: 提供多个串行存取存储器。 动态随机存取存储器（30）被寻址以向其输入数据并从其输出数据。 响应于提供给它的地址信号（34,36,38），从阵列（50）输出数据行。 多个串行输出端口（44,46,48）耦合到阵列的输出端，用于选择性地锁存从阵列输出的不同行数据。 串行输出端口（44,46,48）被定时以从其输出锁存的数据。 在一个图示的实施例中，每个串行输出端口包含一个移位寄存器（62,64,66，... 68），其长度等于存储器阵列（30）的宽度。 移位寄存器响应于第一定时信号（42,52）以锁存来自阵列（30）的一行数据。 第二定时信号致动移位寄存器以移位一行锁存数据。 耦合到移位寄存器的串行访问选择器（70）从串行输出端口输出移位数据的选定部分。 该存储器作为运动补偿帧间图像编码/解码系统的帧存储器具有特殊应用。

公开(公告)号：EP0543197A2

公开(公告)日：1993-05-26

申请号：EP92118660.7

申请日：1992-10-31

Applicant: GENERAL INSTRUMENT CORPORATION OF DELAWARE

Inventor： Shen, Paul ,  Paik, Woo H. ,  Krause, Edward A.

IPC: G11C7/00 ,  G11C11/409

CPC classification number: G11C7/1075 ,  G11C7/1036 ,  H04N19/423 ,  H04N19/433 ,  H04N19/51 ,  H04N19/61

Abstract: A multiple serial access memory is provided. A dynamic random access memory (30) is addressed to input data thereto and output data therefrom. Rows of data are output from the array (50) in response to address signals (34, 36, 38) provided thereto. A plurality of serial output ports (44, 46, 48) is coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports (44, 46, 48) are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register (62, 64, 66, ... 68) having a length equal to the width of the memory array (30). The shift register is responsive to a first timing signal (42, 52) for latching a row of data from the array (30). A second timing signal actuates the shift register to shift a row of latched data. A serial access selector (70) coupled to the shift register outputs a selected portion of the shifted data from the serial output port. The memory has particular application as the frame store for a motion compensated interframe image coding/decoding system.

Abstract translation: 本发明提供一种多串行存取存储器。 一种动态随机存取存储器（30）被从写给向其输入数据和输出数据在那里。 数据行是从在响应所述阵列（50），以解决信号（34，36，38）提供给它的输出。 的串行输出端口（44，46，48）的多个耦合到所述阵列的输出用于选择性地从阵列锁存数据输出的不同的行。 串行输出端口（44，46，48）从时钟到输出锁存的数据在那里。 在图示的实施例中，每个串行输出端口的包含具有等于所述存储器阵列（30）的宽度的长度的移位寄存器（62，64，66，... 68）。 移位寄存器响应于从所述阵列（30）闩锁的一行数据的第一定时信号（42，52）。 第二定时信号致动所述移位寄存器移位锁存一行数据。 耦合到所述移位寄存器的串行访问选择器（70）输出从串行输出端口的移位的数据的所选部分，所述存储器具有特别的应用为帧存储器，用于运动补偿的帧间图像编码/解码系统。