公开(公告)号：WO2016054186A1

公开(公告)日：2016-04-07

申请号：PCT/US2015/053187

申请日：2015-09-30

Applicant: AVNERA CORPORATION

Inventor： KUMAR, Amit ,  IRRGANG, Thomas ,  ZHAO, Xudong

IPC: G10K11/178

CPC classification number: G10K11/17855 ,  G10K11/17881 ,  G10K2210/3051

Abstract: An audio system having low latency includes a digital audio processor as well as sensor inputs coupled to the processor. The sensor inputs may be microphone inputs. The audio processor operates at the same frequency as the sensor inputs, which is typically much higher than an audio signal provided to the audio processor. In some aspects the audio processor operates as a noise cancellation processor and does not include an audio input.

Abstract translation: 具有低延迟的音频系统包括数字音频处理器以及耦合到处理器的传感器输入。 传感器输入可以是麦克风输入。 音频处理器的工作频率与传感器输入的频率相同，传感器输入通常远高于提供给音频处理器的音频信号。 在一些方面，音频处理器用作噪声消除处理器，并且不包括音频输入。

公开(公告)号：WO2018213799A1

公开(公告)日：2018-11-22

申请号：PCT/US2018/033532

申请日：2018-05-18

Applicant: AVNERA CORPORATION

Inventor： LINK, Garry, N. ,  LEE, Wai

IPC: H03F3/45 ,  H03F3/187

Abstract: A circuit can include a first current source, a second current source, and a differential inverter amplifier electrically coupled between the first current source and the second current source. The differential inverter amplifier can include a plurality of load resistors and a plurality of diode-connected metal oxide semiconductor (MOS) clamps configured to limit output swing and minimize common mode disturbances.

公开(公告)号：WO2018148762A2

公开(公告)日：2018-08-16

申请号：PCT/US2018/018075

申请日：2018-02-13

Applicant: AVNERA CORPORATION

Inventor： AN, Jiajin ,  WURTZ, MIchael Jon ,  WURTZ, David ,  KHAIRA, Manpreet ,  KUMAR, Amit ,  O'CONNOR, Shawn ,  RATHOUD, Shankar ,  SCANLAN, James ,  SORENSEN, Eric

IPC: G10L25/78

Abstract: Many headsets include automatic noise cancellation (ANC) which dramatically reduces perceived background noise and improves user listening experience. Unfortunately, the voice microphones in these devices often capture ambient noise that the headsets output during phone calls or other communication sessions to other users. In response, many headsets and communication devices provide manual muting circuitry, but users frequently forget to turn the muting on and/or off, creating further problems as they communicate. To address this, the present inventors devised, among other things, an exemplary headset that detects the absence or presence of user speech, automatically muting and unmuting the voice microphone without user intervention. Some embodiments leverage relationships between feedback and feedforward signals in ANC circuitry to detect user speech, avoiding the addition of extra hardware to the headset. Other embodiments also leverage the speech detection function to activate and deactivate keyword detectors, and/or sidetone circuits, thus extending battery.

公开(公告)号：WO2018081154A1

公开(公告)日：2018-05-03

申请号：PCT/US2017/058128

申请日：2017-10-24

Applicant: AVNERA CORPORATION

Inventor： KUMAR, Amit ,  RATHOUD, Shankar ,  WURTZ, Mike ,  ETHERIDGE, Eric ,  SORENSEN, Eric

IPC: G10K11/178 ,  H04R3/00

Abstract: Disclosed is a signal processor for headphone off-ear detection. The signal processor includes an audio output to transmit an audio signal toward a headphone speaker in a headphone cup. The signal processor also includes a feedback (FB) microphone input to receive a FB signal from a FB microphone in the headphone cup. The signal processor also includes an off-ear detection (OED) signal processor to determine an audio frequency response of the FB signal over an OED frame as a received frequency response. The OED processor also determines an audio frequency response of the audio signal times an off-ear transfer function between the headphone speaker and the FB microphone as an ideal off-ear response. A difference metric si generated comparing the received frequency response to the ideal off-ear frequency response. The difference metric is employed to detect when the headphone cup is disengaged from an ear.

Abstract translation: 公开了一种用于耳机离耳检测的信号处理器。 信号处理器包括音频输出，以向耳机杯中的头戴式耳机扬声器发送音频信号。 信号处理器还包括反馈（FB）麦克风输入，以从头戴式耳机杯中的FB麦克风接收FB信号。 信号处理器还包括用于将OED帧上的FB信号的音频响应确定为接收到的频率响应的非人耳检测（OED）信号处理器。 OED处理器还确定音频信号的音频响应乘以耳机扬声器与FB麦克风之间的非耳朵传递函数，作为理想的非人耳响应。 生成的差值度量si将接收到的频率响应与理想的耳外频率响应进行比较。 采用差异度量来检测耳机杯何时与耳朵分离。

公开(公告)号：WO2017066708A2

公开(公告)日：2017-04-20

申请号：PCT/US2016/057225

申请日：2016-10-14

Applicant: AVNERA CORPORATION

Inventor： KUMAR, Amit ,  IRRGANG, Thomas ,  RATHOUD, Shankar ,  SORENSEN, Eric

IPC: H04R1/10 ,  G10K11/178 ,  H04R29/00

CPC classification number: G10K11/178 ,  G10K11/17813 ,  G10K11/1788 ,  G10K11/17881 ,  G10K2210/1081 ,  G10K2210/3025 ,  G10K2210/3026 ,  G10K2210/3027 ,  G10K2210/3045 ,  G10K2210/3055 ,  G10K2210/3056 ,  G10K2210/3214 ,  G10K2210/504 ,  H04R1/1083 ,  H04R29/00 ,  H04R2460/01

Abstract: A method of calibrating an earphone may include: securing an ANC earphone to a calibration fixture, the calibration fixture including an ear model configured to support the ANC earphone, the ear model having an ear canal configured to anatomically resemble a human ear canal and a concha configured to anatomically resemble a human ear concha, the ear canal extending from the concha to an inner end of the ear canal; generating, with the ANC earphone, an audio signal based on a reference tone; determining a characteristic of the audio signal; comparing the characteristic of the audio signal to a previously determined reference characteristic; and adjusting a gain value of the ANC earphone based on the comparing. Additional methods and apparatus are also disclosed.

Abstract translation: 一种校准耳机的方法可以包括：将ANC耳机固定到校准固定装置，所述校准固定装置包括被配置为支持ANC耳机的耳模型，所述耳模型具有耳道，所述耳道被配置为解剖学地 类似于人耳道和被配置为在解剖学上类似于人耳外耳的耳甲，耳道从耳甲延伸至耳道的内端; 利用ANC耳机生成基于基准音调的音频信号; 确定音频信号的特性; 将音频信号的特性与先前确定的参考特性进行比较; 以及基于该比较调整ANC耳机的增益值。 还公开了其他方法和装置。

公开(公告)号：WO2019060565A1

公开(公告)日：2019-03-28

申请号：PCT/US2018/051979

申请日：2018-09-20

Applicant: AVNERA CORPORATION

Inventor： LEE, Wai, Laing

IPC: H03F3/217 ,  H03M1/50 ,  H03M3/02

Abstract: An amplifier for headphones including a current digital-to-analog converter (DAC) configured to output a current based on a digital audio input signal, an output electrically connected to a speaker and configured to output an output signal to the speaker, and a pulse width modulation (PWM) loop configured to receive an error signal, the error signal based on a difference between the current from the current DAC and a current of the output signal, and generate the output signal based on the error signal. The PWM loop includes an analog-to- digital converter (ADC) configured to receive an analog signal based on the current from the current DAC and output a digital signal representing the analog signal, and an encoder configured to receive the digital signal and output a pulse having a width based on the analog signal.

公开(公告)号：WO2018165550A8

公开(公告)日：2018-09-13

申请号：PCT/US2018/021748

申请日：2018-03-09

Applicant: AVNERA CORPORATION

Inventor： KUMAR, Amit

IPC: G10K11/178

Abstract: The disclosure includes an acoustic processing network comprising a Digital Signal Processor (DSP) operating at a first frequency and a Real-Time Acoustic Processor (RAP) operating at a second frequency higher than the first frequency. The DSP receives a noise signal from at least one microphone. The DSP then generates a noise filter based on the noise signal. The RAP receives the noise signal from the microphone and the noise filter from the DSP. The RAP then generates an anti-noise signal based on the noise signal and the noise filter for use in Active Noise Cancellation (ANC).

公开(公告)号：WO2018119148A1

公开(公告)日：2018-06-28

申请号：PCT/US2017/067731

申请日：2017-12-20

Applicant: AVNERA CORPORATION

Inventor： LEE, Wai ,  WEN, Jianping ,  LINK, Garry, N. ,  LI, Jian

IPC: H03M1/08 ,  H03M1/10 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03M1/462 ,  H03M1/0863 ,  H03M1/1019 ,  H03M1/1061 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/129 ,  H03M1/466 ,  H03M1/468

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a successive approximation register (SAR) unit including one or more capacitive networks. The capacitive networks take a sample of an analog signal. The SAR also includes a comparator to approximate digital values based on the analog signal sample via successive comparison. The ADC includes a preamplifier coupled to the SAR unit. The preamplifier amplifies the analog signal for application to the capacitive networks for sampling. The ADC also includes a rough buffer coupled to the SAR unit. The rough buffer pre-charges the capacitive networks of the SAR unit prior to application of the analog signal from the preamplifier.

公开(公告)号：WO2018119143A1

公开(公告)日：2018-06-28

申请号：PCT/US2017/067724

申请日：2017-12-20

Applicant: AVNERA CORPORATION

Inventor： LEE, Wai ,  WEN, Jianping ,  LINK, Garry, N.

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/46

Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

公开(公告)号：WO2017165696A1

公开(公告)日：2017-09-28

申请号：PCT/US2017/023891

申请日：2017-03-23

Applicant: AVNERA CORPORATION

Inventor： NILSON, Christopher, D.

IPC: G05F1/46

CPC classification number: G05F1/468

Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

Abstract translation: 用于带隙基准电压发生器电路的启动电路包括具有连接到带隙基准电压发生器电路的电源电压的漏极的第一原生晶体管和连接到所述带隙基准电压生成器电路的栅极的源极， 第一本地晶体管; 低电压晶体管，其源极连接到地，漏极连接到第一固有晶体管的源极，栅极连接到电阻器; 具有连接到电阻器的源极的第二原生晶体管，连接到第一原生晶体管的源极的栅极; 漏极连接到第二原生晶体管的漏极并且源极连接到电源电压的高电压晶体管; 以及具有连接到第一高压晶体管的栅极的栅极和为带隙基准电压产生器电路提供启动电流的漏极的晶体管。