公开(公告)号：WO2011066802A1

公开(公告)日：2011-06-09

申请号：PCT/CN2010/079412

申请日：2010-12-03

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD. ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WU, Hsiao Chia ,  LUO, Zehuang ,  HAN, Guangtao

Inventor： WU, Hsiao Chia ,  LUO, Zehuang ,  HAN, Guangtao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7824 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An N type lateral double diffused metal oxide semiconductor (NLDMOS) device comprises a floating P type structure (115), a first field oxide region (107), a second field oxide region (109) and an N type drift region (113), wherein the first field oxide region (107) and the second field oxide region (109) are disposed on the N type drift region (113); the floating P type structure (115) is located in the middle portion of the N type drift region (113); the first field oxide region (107) and the second field oxide region (109) are not connected together; and width of active region between the first field oxide region (107) and the second field oxide region (109) matches with length of the injected floating P type structure (115). By employing the construction of the NLDMOS, not only the breakdown voltage of semiconductor device can be raised, but also on-resistance can be effectively lowered. Meanwhile, the requirements of high-energy injection are lowered and the limitation to processing machine is decreased, making the manufacturing easier to be carried out.

Abstract translation: N型横向双扩散金属氧化物半导体（NLDMOS）器件包括浮置P型结构（115），第一场氧化物区域（107），第二场氧化物区域（109）和N型漂移区域（113） 其中所述第一场氧化物区域和所述第二场氧化物区域设置在所述N型漂移区域上）。 浮动P型结构（115）位于N型漂移区（113）的中间部分; 第一场氧化物区域（107）和第二场氧化物区域（109）不连接在一起; 并且第一场氧化物区域（107）和第二场氧化物区域（109）之间的有源区域的宽度与注入的浮动P型结构（115）的长度相匹配。 通过采用NLDMOS的结构，不仅可以提高半导体器件的击穿电压，而且可以有效降低导通电阻。 同时，降低了高能量喷射的要求，降低了对加工机器的限制，使得制造更容易进行。

公开(公告)号：WO2012083781A1

公开(公告)日：2012-06-28

申请号：PCT/CN2011/082934

申请日：2011-11-25

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  CHENG, Liang

Inventor： CHENG, Liang

IPC: H03K5/24

CPC classification number: H03K5/2472 ,  H03K5/2481

Abstract: The present disclosure provides a voltage comparator including a current source, a differential gain module and a switch module, wherein the magnitude of the current flowing through the current source is nano ampere level; the differential gain module includes a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first transistor and the second transistor are respectively connected to the current source, the third transistor and the fourth transistor form a mirror current structure, the third transistor is connected to the first transistor, and the fourth transistor is connected to the second transistor via a ninth transistor used for forming asymmetric differential gain.

Abstract translation: 本公开提供了一种电压比较器，其包括电流源，差分增益模块和开关模块，其中流过电流源的电流的大小为纳安电平; 差分增益模块包括第一晶体管，第二晶体管，第三晶体管和第四晶体管，其中第一晶体管和第二晶体管分别连接到电流源，第三晶体管和第四晶体管形成镜电流结构， 第三晶体管连接到第一晶体管，并且第四晶体管经由用于形成非对称差分增益的第九晶体管连接到第二晶体管。

公开(公告)号：WO2012079463A1

公开(公告)日：2012-06-21

申请号：PCT/CN2011/083240

申请日：2011-11-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WU, Hsiaochia ,  GUO, Li ,  HAN, Guangtao ,  YAN, Jian

Inventor： WU, Hsiaochia ,  GUO, Li ,  HAN, Guangtao ,  YAN, Jian

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/265 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/7833

Abstract: A complementary metal-oxide semiconductor (CMOS) device is disclosed. The CMOS device includes a substrate, a well region formed in the substrate, and a gate formed on the substrate. The CMOS device also includes a first region and a second region formed in the well region and arranged at two sides of the gate. Further, the CMOS device includes a first light-doped drain (LDD) region and a second LDD region formed in the well region and extending the first region and the second region, respectively, towards the gate. The CMOS device also includes a first doped layer formed in the first LDD region, and a conduction type of an ion doped in the first doped layer is opposite to a conduction type of an ion doped in the first LDD region.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件。 CMOS器件包括衬底，形成在衬底中的阱区和形成在衬底上的栅极。 CMOS器件还包括形成在阱区中并布置在栅极两侧的第一区和第二区。 此外，CMOS器件包括形成在阱区中的第一掺光漏极（LDD）区域和第二LDD区域，并分别朝向栅极延伸第一区域和第二区域。 CMOS器件还包括形成在第一LDD区域中的第一掺杂层，并且掺杂在第一掺杂层中的导电类型与在第一LDD区域中掺杂的离子的导电类型相反。

公开(公告)号：WO2012075896A1

公开(公告)日：2012-06-14

申请号：PCT/CN2011/083120

申请日：2011-11-29

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  LEI, Shunhui

Inventor： LEI, Shunhui

IPC: H02H7/18 ,  H02H7/00

CPC classification number: H02H7/18 ,  H02J7/0029 ,  H02J7/0031 ,  H02J2007/0039 ,  Y02E60/12

Abstract: A lithium battery protection circuit coupled to a lithium battery is provided. The lithium battery protection circuit includes an over-charge protection circuit and a logic circuit coupled to over-charge protection circuit. The logic circuit has a first logic output and a second logic output. The lithium battery protection circuit also includes a level shift circuit coupled to the logic circuit through the first logic output and the second logic output, and the level shift circuit is configured to convert the first logic output and the second logic output to high voltage levels in an over-charge protection state. Further, the lithium battery protection circuit includes a substrate switching circuit coupled to the level shift circuit and a power transistor coupled between a negative end of the lithium battery and an external circuit negative electrode. The level shift circuit includes a first inverter coupled to the second logic output, a plurality of PMOS transistors, at least one of which has high source-drain voltage and low gate-source voltage, and a plurality of NMOS transistors, at least one of which is a low-voltage NMOS transistor.

Abstract translation: 提供耦合到锂电池的锂电池保护电路。 锂电池保护电路包括过充电保护电路和耦合到过充电保护电路的逻辑电路。 逻辑电路具有第一逻辑输出和第二逻辑输出。 锂电池保护电路还包括通过第一逻辑输出和第二逻辑输出耦合到逻辑电路的电平移位电路，并且电平移位电路被配置为将第一逻辑输出和第二逻辑输出转换成高电压电平 过充保护状态。 此外，锂电池保护电路包括耦合到电平移位电路的衬底切换电路和耦合在锂电池的负端和外部电路负极之间的功率晶体管。 电平移位电路包括耦合到第二逻辑输出的第一反相器，多个PMOS晶体管，其至少其中之一具有高源极 - 漏极电压和低栅极 - 源极电压，以及多个NMOS晶体管，至少一个 其是低电压NMOS晶体管。

公开(公告)号：WO2012071987A1

公开(公告)日：2012-06-07

申请号：PCT/CN2011/082400

申请日：2011-11-18

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  DU, Jian ,  LI, Jiajia ,  FANG, Hao

Inventor： DU, Jian ,  LI, Jiajia ,  FANG, Hao

IPC: H01L21/02

CPC classification number: H01L23/291 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/28238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed for manufacturing a semiconductor device. The method includes providing a substrate and forming a well region in the substrate by an ion implantation. The method also includes forming, by rapid thermal oxidation and on the substrate having the well region, an oxide layer for repairing the substrate damaged by the ion implantation. Further, the method includes removing the oxide layer and forming a gate oxide layer on the repaired substrate having the well region.

Abstract translation: 公开了制造半导体器件的方法。 该方法包括提供衬底并通过离子注入在衬底中形成阱区。 该方法还包括通过快速热氧化和在具有阱区的基板上形成用于修复由离子注入损坏的衬底的氧化物层。 此外，该方法包括去除氧化物层并在具有阱区的修复的衬底上形成栅极氧化物层。

公开(公告)号：WO2012068971A1

公开(公告)日：2012-05-31

申请号：PCT/CN2011/082428

申请日：2011-11-18

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  CHENG, Liang

Inventor： CHENG, Liang

IPC: H03F3/45

CPC classification number: H03F3/45192 ,  H03F3/3016 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45183 ,  H03F2200/456 ,  H03F2203/45248 ,  H03F2203/45264 ,  H03F2203/45308 ,  H03F2203/45352 ,  H03F2203/45526 ,  H03F2203/45674 ,  H03F2203/45692

Abstract: A folded cascode operational amplifier is disclosed. The folded cascode operational amplifier includes a first current source(M1), a second current source(M2), and a first voltage terminal(VDD) connected to the first current source(M1) and the second current source (M2). The folded cascode operational amplifier also includes a first input-transistor(M4) connected to the first current source(M1) in series, and a second input-transistor(M5) connected to the second current source(M2) in series. Further, the folded cascode operational amplifier includes a tail current source(M3) connected to a connection point between the first input-transistor(M4) and the second input-transistor(M5), a load current source(M7), and a second voltage terminal(VSS) connected to the tail current source(M3) and the load current source(M7). The folded cascode operational amplifier also includes an output-transistor (M6) connected to the load current source(M7), and an output-terminal(202) arranged between the second current source(M2) and the second input-transistor(M5) and connected to the output-transistor(M6). The second current source(M2) is a mirroring current source of the first current source(M1), and a ratio of a current passing through the second current source(M2) to a current passing through the first current source(M1) is greater than one.

Abstract translation: 公开了折叠共源共栅运算放大器。 折叠共源共栅运算放大器包括第一电流源（M1），第二电流源（M2）和连接到第一电流源（M1）和第二电流源（M2）的第一电压端子（VDD）。 折叠共源共栅运算放大器还包括串联连接到第一电流源（M1）的第一输入晶体管（M4）和串联连接到第二电流源（M2）的第二输入晶体管（M5）。 此外，折叠共源共栅运算放大器包括连接到第一输入晶体管（M4）和第二输入晶体管（M5）之间的连接点的负载电流源（M3），负载电流源（M7）和第二 电压端子（VSS）连接到尾电流源（M3）和负载电流源（M7）。 折叠共源共栅运算放大器还包括连接到负载电流源（M7）的输出晶体管（M6）和布置在第二电流源（M2）和第二输入晶体管（M5）之间的输出端子（202） 并连接到输出晶体管（M6）。 第二电流源（M2）是第一电流源（M1）的镜像电流源，并且通过第二电流源（M2）的电流与通过第一电流源（M1）的电流的比值更大 比一个。

公开(公告)号：WO2012062175A1

公开(公告)日：2012-05-18

申请号：PCT/CN2011/081718

申请日：2011-11-03

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WANG, Le

Inventor： WANG, Le

IPC: H01L21/70 ,  H01L21/02

CPC classification number: H01L29/66484 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823468

Abstract: A method for manufacturing a double-gate structure is provided. The method includes providing a substrate; forming a first gate region (201) on a surface of the substrate using a first gate layer; forming a second gate layer which covers the first gate layer on the surface of the substrate; forming an etch-stop layer (203) on the second gate layer; forming a silicide layer (205) on the etch-stop layer (203); and forming a second gate region, different from the first gate region (201), containing the second gate layer and the silicide layer (205) without the etch-stop layer (203). The etch-stop layer (203) is arranged between the second gate layer and the silicide layer (205) to facilitate even etching of the second gate layer around the first gate region (201).

Abstract translation: 提供一种制造双栅结构的方法。 该方法包括提供基板; 使用第一栅极层在所述衬底的表面上形成第一栅极区域（201）; 形成覆盖所述基板表面上的所述第一栅极层的第二栅极层; 在所述第二栅极层上形成蚀刻停止层（203）; 在所述蚀刻停止层（203）上形成硅化物层（205）; 以及形成不含有所述第二栅极层和不具有所述蚀刻停止层（203）的所述硅化物层（205）的与所述第一栅极区域（201）不同的第二栅极区域。 蚀刻停止层（203）被布置在第二栅极层和硅化物层（205）之间以促进围绕第一栅极区域（201）的第二栅极层的均匀蚀刻。

公开(公告)号：WO2012034372A1

公开(公告)日：2012-03-22

申请号：PCT/CN2011070950

申请日：2011-02-12

Applicant: CSMC TECHNOLOGIES FAB1 CO LTD ,  CSMC TECHNOLOGIES FAB2 CO LTD ,  WANG GENYI ,  WO TZONG SHIANN

Inventor： WANG GENYI ,  WO TZONG SHIANN

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

Abstract: A trench vertical double diffused metal oxide semiconductor transistor includes, in part, a semiconductor substrate, an epitaxial layer formed above the substrate, a well region formed in the epitaxial layer, a multitude of trenches formed in the well region with each trench having formed therein a gate oxide layer and a polysilicon gate, a multitude of contact holes formed in the well region wherein each contact hole is positioned between a pair of adjacent trenches and has a metal disposed therein, a multitude of body contact regions positioned below the contact holes, and a multitude of source regions formed in the well region. Each source region is positioned between a trench and a contact hole. The substrate, the epitaxial layer, and the source regions are of the first conductivity type. The well region and the body contact regions are of the second conductivity type opposite the first conductivity type.

Abstract translation: 沟槽垂直双扩散金属氧化物半导体晶体管部分地包括半导体衬底，形成在衬底上方的外延层，形成在外延层中的阱区，形成在阱区中的多个沟槽，其中形成有每个沟槽 栅极氧化物层和多晶硅栅极，阱区中形成有多个接触孔，其中每个接触孔位于一对相邻的沟槽之间并且具有设置在其中的金属，多个体接触区域位于接触孔下方， 以及在阱区中形成的多个源极区。 每个源极区位于沟槽和接触孔之间。 衬底，外延层和源极区域是第一导电类型。 阱区和体接触区具有与第一导电类型相反的第二导电类型。

公开(公告)号：WO2012034371A1

公开(公告)日：2012-03-22

申请号：PCT/CN2011/070949

申请日：2011-02-12

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD. ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WANG, Genyi ,  WO, Tzong Shiann

Inventor： WANG, Genyi ,  WO, Tzong Shiann

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

Abstract: A metal oxide semiconductor (MOS) transistor (200) includes, in part, a semiconductor substrate (201), an epitaxial layer (202) formed above the substrate (201), a well region (203) formed in the epitaxial layer (202), a multitude of trenches (210) formed in the well region (203) with each trench (210) having formed therein a gate oxide layer (212) and a polysilicon gate (211), a multitude of contact holes (220) formed in the well region (203) wherein each contact hole (220) is positioned between a pair of adjacent trenches (210) and has disposed therein an adhesion layer (232) and a first metal layer (233) forming a metal plug, a multitude of body contact regions (204) positioned below the contact holes (220), and a multitude of source regions (231) formed in the well region (203). Each source region (231) is positioned between a trench (210) and a contact hole (220). The substrate (201), the epitaxial layer (202), and the source regions (231) are of a first conductivity type. The well region (203) and the body contact regions (204) are of a second conductivity type opposite the first conductivity type. The MOS transistor can minimize various parasitic effects and improve performance thereof. A method is also provided.

Abstract translation: 金属氧化物半导体（MOS）晶体管（200）部分地包括半导体衬底（201），形成在衬底（201）上方的外延层（202），形成在外延层（202）中的阱区 ），形成在阱区（203）中的多个沟槽（210），其中每个沟槽（210）中形成有栅极氧化物层（212）和多晶硅栅极（211），形成多个接触孔（220） 在井区域（203）中，其中每个接触孔（220）位于一对相邻的沟槽（210）之间，并且在其中设置有粘合层（232）和形成金属插塞的第一金属层（233） 位于所述接触孔（220）下方的身体接触区域（204）以及形成在所述阱区域（203）中的多个源极区域（231）。 每个源极区域（231）位于沟槽（210）和接触孔（220）之间。 衬底（201），外延层（202）和源极区（231）是第一导电类型。 阱区（203）和体接触区（204）具有与第一导电类型相反的第二导电类型。 MOS晶体管可以最小化各种寄生效应并提高其性能。 还提供了一种方法。

公开(公告)号：WO2012079483A1

公开(公告)日：2012-06-21

申请号：PCT/CN2011/083632

申请日：2011-12-07

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  CHENG, Liang

Inventor： CHENG, Liang

IPC: H03F3/217

CPC classification number: H03F3/217 ,  H03F2200/351 ,  H03K5/2481

Abstract: A pulse width modulation (PWM) comparator and a Class D amplifier are provided. In the PWM comparator, a current feedback mechanism is introduced, which is based on a waveform state of a received high frequency triangle signal and a level state of an output signal of the PWM comparator. The hysteresis of the PWM comparator is changed dynamically, so that the noise resistance ability of the PWM comparator is much better than that of the conventional PWM comparators having a fixed hysteresis. The PWM comparator can operate stably even if the duty cycle of the output signal is nearly 100%.

Abstract translation: 提供脉宽调制（PWM）比较器和D类放大器。 在PWM比较器中，引入电流反馈机制，其基于接收的高频三角形信号的波形状态和PWM比较器的输出信号的电平状态。 PWM比较器的滞后动态变化，使得PWM比较器的抗噪声能力比具有固定滞后的常规PWM比较器的噪声阻抗能力好得多。 即使输出信号的占空比接近100％，PWM比较器也能稳定运行。