公开(公告)号：JP2009032803A

公开(公告)日：2009-02-12

申请号：JP2007193550

申请日：2007-07-25

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： MATSUDA KEITA

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/423 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475

Abstract: PROBLEM TO BE SOLVED: To suppress the leakage current of a Schottky junction. SOLUTION: This invention discloses the field effect transistor comprising a nitride semiconductor layer including a channel layer, a Schottky electrode 20 including a GZO layer 22 provided in contact with the nitride semiconductor layer and heat-treated under an inert gas atmosphere and ohmic electrodes 16 and 18 connected to the channel layer, and its manufacturing method. By this invention, by forming the Schottky junction of the nitride semiconductor layer and the GZO layer 22, the leakage current of the reverse current of the Schottky junction is suppressed and the ideal coefficient of a forward current is brought close to 1. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：抑制肖特基结的泄漏电流。 解决方案：本发明公开了包括具有沟道层的氮化物半导体层的场效应晶体管，包括与氮化物半导体层接触并在惰性气体气氛下热处理的GZO层22的肖特基电极20和欧姆 连接到沟道层的电极16和18及其制造方法。 通过本发明，通过形成氮化物半导体层和GZO层22的肖特基结，抑制肖特基结的反向电流的漏电流，使正向电流的理想系数接近1。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008288397A

公开(公告)日：2008-11-27

申请号：JP2007132193

申请日：2007-05-17

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： YUI KEIICHI

IPC: H01L33/06 ,  H01L33/32

CPC classification number: H01L33/32 ,  H01L33/06

Abstract: PROBLEM TO BE SOLVED: To improve light emission efficiency in a semiconductor light-emitting apparatus. SOLUTION: A semiconductor light-emitting apparatus comprises a substrate and a quantum well active layer which comprises a plurality of barrier layers 32 composed of a GaN-based semiconductor and a well layer 30 sandwiched between the barrier layers 32 and composed of the GaN-based semiconductor and which has a polarization charge formed by piezo polarization between the barrier layer 32 and the well layer 30. In the semiconductor light-emitting apparatus, the well layer 30 is formed by modulating the composition so that a handicap becomes minimum at an interface with the barrier layer 32 on a side farther from the substrate 10. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提高半导体发光装置的发光效率。 解决方案：半导体发光装置包括基板和量子阱有源层，其包括由GaN基半导体构成的多个势垒层32和夹在势垒层32之间的阱层30，并由 GaN基半导体，其具有通过势垒层32和阱层30之间的压电极化形成的极化电荷。在半导体发光装置中，阱层30通过调制组​​成使得障碍物在 与位于离衬底10更远的一侧的阻挡层32的界面。版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008251881A

公开(公告)日：2008-10-16

申请号：JP2007092026

申请日：2007-03-30

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： HANAWA IKUO ,  DOMOTO SHINICHI ,  ARAI MORITA

IPC: H01L31/107 ,  H01L31/10

Abstract: PROBLEM TO BE SOLVED: To provide a light-receiving element capable of reducing a dark current, and to provide a manufacturing method thereof.
SOLUTION: The light-receiving element (100) is provided with a semiconductor substrate (1); first conductivity-type first semiconductor layers (2, 3, 4, 5 and 6) provided on the semiconductor substrate; a second conductivity-type second semiconductor layer (7) provided on the first semiconductor layers; and a third semiconductor layer (13) provided on the side surfaces of the first semiconductor layers and the second semiconductor layer and equipped with a thin layer region having a thin layer thickness on one part. The thinnest portion of a thin layer region (13a) is positioned on the semiconductor substrate side than a built-in depletion layer (A) on an interface between the first semiconductor layers and the second semiconductor layer.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供能够减少暗电流的光接收元件，并提供其制造方法。 光接收元件（100）设置有半导体衬底（1）; 设置在半导体衬底上的第一导电型第一半导体层（2,3,4,5和6） 设置在所述第一半导体层上的第二导电型第二半导体层（7） 以及设置在第一半导体层和第二半导体层的侧表面上并且在一个部分上具有薄层厚度的薄层区域的第三半导体层（13）。 薄层区域（13a）的最薄部分位于半导体衬底侧上，而不是位于第一半导体层和第二半导体层之间的界面上的内置耗尽层（A）。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008182158A

公开(公告)日：2008-08-07

申请号：JP2007016129

申请日：2007-01-26

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： NAITO KOHEI

IPC: H01L21/338 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L27/0605 ,  H01L27/085 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To suppress a side-gate effect, by setting a p-type semiconductor layer under an element separation region as the electric potential of an FET source electrode.
SOLUTION: The semiconductor device has the p-type semiconductor layer 12 formed on a substrate 10 and comprising a compound semiconductor; a compound semiconductor layer 21 formed on the p-type semiconductor layer 12; a plurality of active regions 27, formed on the compound semiconductor layer 21 and lying adjacent via an element isolation region 28; a connection part 32, connected to the p-type semiconductor layer 12 in the region between the active regions 27, or in the element isolation region 28 adjacent to the region between the active regions 27; and a plurality of FETs 40, 42 respectively formed in the adjacent active regions 27, with the source electrode 22 of at least one FET 42 from among a plurality of FETs connected to the electric potential of the connection part 32, in a region other than the active regions 27.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：通过将元件分离区域下的p型半导体层设定为FET源电极的电位来抑制侧栅效应。 解决方案：半导体器件具有形成在衬底10上并包含化合物半导体的p型半导体层12; 形成在p型半导体层12上的化合物半导体层21; 多个有源区27，形成在化合物半导体层21上并通过元件隔离区28相邻; 在活性区域27之间的区域中或与活性区域27之间的区域相邻的元件隔离区域28中连接到p型半导体层12的连接部分32; 以及分别形成在相邻的有源区域27中的多个FET 40,42，其中来自连接到连接部分32的电位的多个FET中的至少一个FET42的源极22在除了 活跃区域27.版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008166349A

公开(公告)日：2008-07-17

申请号：JP2006351436

申请日：2006-12-27

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： MAKABE ISAO ,  NAKADA TAKESHI

IPC: H01L21/338 ,  H01L21/205 ,  H01L29/778 ,  H01L29/812 ,  H01L33/32 ,  H01L33/34 ,  H01S5/183 ,  H01S5/323

CPC classification number: H01L29/205 ,  H01L29/7786 ,  H01L33/32

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor substrate and a semiconductor device including a GaN layer having a good crystal property and assuring a small warpage. SOLUTION: The semiconductor substrate and semiconductor device include an AIN layer 12 provided on a Si substrate 10, an AlGaN layer 14 provided on the AIN layer 12 to have a composition ratio of Al of 0.3 or more and 0.6 or less, and a GaN layer 16 provided on an AlGaN layer 14. According to the semiconductor substrate and semiconductor device, wafer warpage can be reduced by setting the Al composition ratio of the AlGaN layer 14 to 0.6 or less and GaN layer crystal property can be improved by setting the composition ratio to 0.3 or more. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体衬底和包括具有良好晶体性质的GaN层并确保小翘曲的半导体器件。 解决方案：半导体衬底和半导体器件包括设置在Si衬底10上的AlN层12，设置在AlN层12上的AlGaN层14，其Al的组成比为0.3以上且0.6以下，Al 设置在AlGaN层14上的GaN层16.根据半导体衬底和半导体器件，通过将AlGaN层14的Al组成比设定为0.6以下，可以降低晶片翘曲，并且可以通过设置GaN层16来提高GaN层的晶体性质 组成比为0.3以上。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008141005A

公开(公告)日：2008-06-19

申请号：JP2006326123

申请日：2006-12-01

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： HORINO KAZUHIKO

IPC: H01L21/205 ,  C30B25/02 ,  C30B29/38 ,  H01L33/32

CPC classification number: H01L21/0262 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02576

Abstract: PROBLEM TO BE SOLVED: To improve characteristics in a semiconductor device by reducing edge dislocation in the GaN layer of a semiconductor substrate. SOLUTION: The semiconductor substrate has: an AlN layer 12 provided on a substrate 10; an Si-doped GaN layer 14 provided on the AlN layer 12; and an undoped GaN layer 16 provided on the Si-doped GaN layer 14. By the semiconductor substrate, the semiconductor device, and a method for manufacturing the semiconductor device, edge dislocation in the GaN layer is reduced, thus improving characteristics in the semiconductor device. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：通过减少半导体衬底的GaN层中的边缘位错来改善半导体器件的特性。 解决方案：半导体衬底具有：设置在衬底10上的AlN层12; 设置在AlN层12上的Si掺杂GaN层14; 以及设置在Si掺杂GaN层14上的未掺杂的GaN层16.通过半导体衬底，半导体器件以及半导体器件的制造方法，GaN层中的边缘位错减小，从而改善了半导体器件的特性 。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008130949A

公开(公告)日：2008-06-05

申请号：JP2006316508

申请日：2006-11-24

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： MATSUDA KEITA

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/2003 ,  H01L29/47 ,  H01L29/66462 ,  H01L29/66848 ,  H01L29/7786 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To suppress leakage current at a Schottky junction. SOLUTION: The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device is provided with: a nitride semiconductor layer including a channel layer; a Schottky electrode, containing indium 20, provided in contact with the nitride semiconductor layer; and ohmic electrodes 16, 18 provided in connection with the channel layer. According to the present invention, by forming a Schottky junction of a nitride semiconductor layer and a layer containing indium makes it possible to suppress the reverse leakage current in a Schottky junction and bring the ideal factor of forward current close to 1. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了抑制肖特基结的泄漏电流。 解决方案：半导体器件及半导体器件的制造方法技术领域本发明涉及一种半导体器件的制造方法，其中半导体器件具备：包括沟道层的氮化物半导体层; 设置为与氮化物半导体层接触的包含铟20的肖特基电极; 以及与沟道层连接设置的欧姆电极16,18。 根据本发明，通过形成氮化物半导体层的肖特基结和含有铟的层，可以抑制肖特基结中的反向漏电流，并使正向电流的理想系数接近1。 （C）2008，JPO＆INPIT

公开(公告)号：JP2008130875A

公开(公告)日：2008-06-05

申请号：JP2006315271

申请日：2006-11-22

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： FURUYA AKIRA ,  SEKIGUCHI HIROSHI

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/38 ,  H01L33/62

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device which is excellent in a light-emitting efficiency and mass productivity and uses a transparent insulating substrate whose flip chip bonding can be easily made, and to provide its manufacturing method. SOLUTION: The semiconductor light-emitting device is constructed in a manner such that a first semiconductor layer (14) , an active layer (16), and a second semiconductor layer (18) which is an opposite conductive type to the first semiconductor layer are located on the surface of the transparent insulating substrate (12) having a first cutout portion (20) communicating from the surface side to the back side on the side, and an n-side contact electrode (22) located on the first semiconductor layer and a first electrode (32) located on the back of the transparent insulating substrate are electrically connected through a first connection portion (30) positioned on the first cutout portion, thereby, the first semiconductor layer and the first electrode are electrically connected, and a p-side contact electrode (34) electrically connected with the second semiconductor layer and a second electrode (36) are located on the second semiconductor layer. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供一种发光效率和批量生产率优异的半导体发光装置，并且使用可以容易地制造倒装芯片接合的透明绝缘基板，并提供其制造方法。 解决方案：半导体发光器件以如下方式构成：第一半导体层（14），有源层（16）和第二半导体层（18）与第一半导体层 半导体层位于透明绝缘基板（12）的表面上，该透明绝缘基板（12）具有从侧面的表面侧向背面侧连通的第一切口部（20），位于第一侧的n侧接触电极 半导体层和位于透明绝缘基板背面的第一电极（32）通过位于第一切口部分上的第一连接部分（30）电连接，由此第一半导体层和第一电极电连接， 与第二半导体层电连接的p侧接触电极（34）和第二电极（36）位于第二半导体层上。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008112868A

公开(公告)日：2008-05-15

申请号：JP2006294935

申请日：2006-10-30

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： YAEGASHI SEIJI

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/7786 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462

Abstract: PROBLEM TO BE SOLVED: To suppress leakage current of a GaN-based FET using the MIS structure.
SOLUTION: The GaN-based FET using the MIS structure comprises a GaN electron traveling layer (12) provided on a substrate (10), an AlGaN electron supplying layer (14) provided on the electron traveling layer (12) and generating a two-dimensional electron gas (13) on the electron traveling layer (12), an insulating film (22) provided on the electron supplying layer (14), and a gate electrode (34) provided on the insulating film (22). The film thickness of the insulating film (22) under the center of the gate electrode (34) of the semiconductor device is thinner than that of an insulating film (24) under the end part (35) of the gate electrode (34).
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了抑制使用MIS结构的GaN系FET的漏电流。 解决方案：使用MIS结构的GaN基FET包括设置在基板（10）上的GaN电子传输层（12），设置在电子传播层（12）上的AlGaN电子供给层（14），并产生 电子传播层（12）上的二维电子气（13），设置在电子供给层（14）上的绝缘膜（22）和设在绝缘膜（22）上的栅电极（34）。 半导体器件的栅电极（34）的中心下方的绝缘膜（22）的膜厚比栅电极（34）的端部（35）下方的绝缘膜（24）薄。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008098456A

公开(公告)日：2008-04-24

申请号：JP2006279351

申请日：2006-10-13

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KOSAKA TOSHIYUKI ,  KOMATANI TSUTOMU

IPC: H01L21/3065 ,  H01L21/3205 ,  H01L23/52

CPC classification number: H01L21/0445 ,  H01L21/0332 ,  H01L21/76898

Abstract: PROBLEM TO BE SOLVED: To suppress warping, breaking, cracking, or the like of a substrate which is caused by a difference in thermal expansion factors between the substrate and a metal mask.
SOLUTION: The manufacturing method of a semiconductor device includes a process for forming a metal mask comprising a first trimming pattern (30) for opening a wanted region and a second trimming pattern (32) for opening such region as separates the material of metal mask into a plurality of sections that are not connected each other, and a process for selectively removing at least either a substrate or a layer provided on the substrate by dry-etching using the metal mask.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：抑制由基板和金属掩模之间的热膨胀因子的差异引起的基板的翘曲，断裂或开裂等。 解决方案：半导体器件的制造方法包括用于形成金属掩模的工艺，该金属掩模包括用于打开所需区域的第一修整图案（30）和用于打开所述区域的第二修整图案（32） 金属掩模形成彼此不连接的多个部分，以及通过使用金属掩模的干法蚀刻来选择性地去除设置在基板上的基板或层中的至少一个的工艺。 版权所有（C）2008，JPO＆INPIT