公开(公告)号：WO2010024932A3

公开(公告)日：2010-08-12

申请号：PCT/US2009004916

申请日：2009-08-29

Applicant: GLOBALFOUNDRIES INC ,  MEYER ANDREAS ,  LEHR MATTHIAS ,  KUECHENMEISTER FRANK

Inventor： MEYER ANDREAS ,  LEHR MATTHIAS ,  KUECHENMEISTER FRANK

IPC: H01L23/24 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L24/85 ,  H01L21/56 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48847 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: The wire bond structure of sophisticated metallization systems, for instance based on copper, may be provided without a terminal aluminum layer and without any passivation layers for exposed copper surfaces (212S) by providing a fill material (250) after the wire bonding process in order to encapsulate at least the sensitive metal surfaces (212S) and a portion of the bond wire (230). Hence, significant cost reduction, reduced cycle times and a reduction of the required process steps may be accomplished independently from the wire bond materials used. Thus, integrated circuits requiring a sophisticated metallization system may be connected by wire bonding to the corresponding package (260) or carrier substrate with a required degree of reliability based on a corresponding fill material (250) for encapsulating at least the sensitive metal surfaces (212S).

Abstract translation: 通过在引线接合工艺之后提供填充材料（250），可以提供例如基于铜的精密金属化系统的引线接合结构，而无需端子铝层并且没有用于暴露的铜表面（212S）的任何钝化层 以封装至少敏感金属表面（212S）和一部分键合线（230）。 因此，显着的成本降低，减少的循环时间和所需的工艺步骤的减少可独立于所使用的丝焊材料来实现。 因此，基于用于封装至少敏感金属表面（212S）的相应填充材料（250），需要精密金属化系统的集成电路可以通过引线接合与具有所需可靠程度的可靠程度的相应封装（260） ）。

公开(公告)号：WO2010085757A1

公开(公告)日：2010-07-29

申请号：PCT/US2010/021999

申请日：2010-01-25

Applicant: GLOBALFOUNDRIES INC. ,  PAL, Rohit ,  YANG, Frank Bin

Inventor： PAL, Rohit ,  YANG, Frank Bin

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84

Abstract: Methods of fabricating a semiconductor device (100) on and in a semiconductor substrate (110) having a first region (180) and a second region (200) are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack (124) overlying the first region (180) and a second gate stack (128) overlying the second region (200), etching into the substrate (110) first recesses (142) and second recesses (142), the first recesses (142) aligned at least to the first gate stack (124) in the first region (180), and the second recesses (142) aligned at least to the second gate stack (128) in the second region (200), epitaxially growing a first stress-inducing monocrystalline material (150) in the first and second recesses (142), removing the first stress-inducing monocrystalline material (150) from the first recesses (142), and epitaxially growing a second stress-inducing monocrystalline material (170) in the first recesses (142), wherein the second stress-inducing monocrystalline material (170) has a composition different from the first stress-inducing monocrystalline material (150).

Abstract translation: 提供了在具有第一区域（180）和第二区域（200）的半导体衬底（110）之上和之中制造半导体器件（100）的方法。 根据本发明的示例性实施例，一种方法包括形成覆盖第一区域（180）的第一栅极堆叠（124）和覆盖第二区域（200）的第二栅极叠层（128），蚀刻到衬底（110） ）第一凹部（142）和第二凹部（142），所述第一凹部（142）至少对准所述第一区域（180）中的所述第一栅极堆叠（124），并且所述第二凹部（142）至少对准 在第二区域（200）中的第二栅极堆叠（128），在第一和第二凹部（142）中外延生长第一应力诱导单晶材料（150），从第一和第二区域移除第一应力诱导单晶材料（150） 凹陷（142），并且在第一凹槽（142）中外延生长第二应力诱导单晶材料（170），其中第二应力诱导单晶材料（170）具有不同于第一应力诱导单晶材料 150）。

公开(公告)号：WO2010062385A1

公开(公告)日：2010-06-03

申请号：PCT/US2009/006276

申请日：2009-11-25

Applicant: GLOBALFOUNDRIES INC. ,  BEYER, Sven ,  PRESS, Patrick ,  GIEDIGKEIT, Rainer ,  HOENTSCHEL, Jan

Inventor： BEYER, Sven ,  PRESS, Patrick ,  GIEDIGKEIT, Rainer ,  HOENTSCHEL, Jan

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795

Abstract: In a multiple gate transistor, the plurality of fins of the drain or source (211) of the transistor (200) are electrically connected to each other by means of a common contact element (243), wherein enhanced uniformity of the corresponding contact regions (235) may be accomplished by an enhanced silicidation process sequence. For this purpose, the fins may be embedded into a dielectric material (230) in which an appropriate contact opening (230A) may be formed to expose end faces (210F) of the fins (210), which may then act as silicidation surface areas.

Abstract translation: 在多栅极晶体管中，晶体管（200）的漏极或源极（211）的多个散热片通过公共接触元件（243）彼此电连接，其中相应的接触区域（ 235）可以通过增强的硅化工艺顺序完成。 为此，翅片可嵌入介电材料（230）中，其中可以形成适当的接触开口（230A）以暴露翅片（210）的端面（210F），其然后可以作为硅化表面区域 。

公开(公告)号：WO2009094163A3

公开(公告)日：2009-07-30

申请号：PCT/US2009/000410

申请日：2009-01-22

Applicant: GLOBALFOUNDRIES INC. ,  SEREBRIN, Benjamin, C. ,  HAERTEL, Michael, J.

Inventor： SEREBRIN, Benjamin, C. ,  HAERTEL, Michael, J.

IPC: G06F9/445

Abstract: In one embodiment, a processor (30) supports an alternate address space during execution of non-guest code (such as a minivisor (172) or a virtual machine monitor (VMM) (18)). The alternate address space may be the guest address space. An instruction in the minivisor ( 172)/VMM (18) may specify the alternate address space for a data access, permitting the minivisor (172) /VMM (18) to read guest memory state via the alternate address space. In another embodiment, a processor (30) may implement a page table base address register (mCR3) dedicated for the minivisor's (172) use. In still another embodiment, the minivisor (172) may be implemented as a specified entry point in the VMM address space (220).

公开(公告)号：WO2011013091A3

公开(公告)日：2011-11-03

申请号：PCT/IB2010053457

申请日：2010-07-29

Applicant: GLOBALFOUNDRIES INC ,  WALTER AXEL ,  LEHR MATTHIAS

Inventor： WALTER AXEL ,  LEHR MATTHIAS

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L23/481 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06133 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer (260), which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer (260) comprises copper-based buffer regions (265) that cover a significant portion of the overall surface, wherein a thickness of approximately 3- 10 µm may also be used. Moreover, the buffer regions (265) may efficiently replace aluminum as a terminal metal active region.

Abstract translation: 形成在复杂半导体器件的金属化系统上方的凸块结构或柱结构可以包括应力缓冲层（260），该应力缓冲层可以有效地分布由于这些芯片封装相互作用期间的热失配而可能通常发生的机械应力 组件。 应力缓冲层（260）包括覆盖整个表面的显着部分的铜基缓冲区（265），其中也可以使用大约3至10μm的厚度。 而且，缓冲区（265）可以有效地替代铝作为端金属活性区域。

公开(公告)号：WO2011013080A1

公开(公告)日：2011-02-03

申请号：PCT/IB2010/053437

申请日：2010-07-28

Applicant: GLOBALFOUNDRIES INC. ,  KAMMLER, Thorsten ,  WIATR, Maciej ,  BOSCHKE, Roman ,  JAVORKA, Peter

Inventor： KAMMLER, Thorsten ,  WIATR, Maciej ,  BOSCHKE, Roman ,  JAVORKA, Peter

IPC: H01L21/8238 ,  H01L21/8239 ,  H01L21/8244 ,  H01L27/02 ,  H01L27/105 ,  H01L27/11 ,  H01L21/768

CPC classification number: H01L21/823871 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104

Abstract: In a static memory cell, the failure rate upon forming contact elements connecting an active region (202C) with a gate electrode structure (210A) formed above an isolation region (203) may be significantly reduced by incorporating an implantation species at a tip portion of the active region (202C) through a sidewalS (203S) of the isolation trench (203T) prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region (202C),

Abstract translation: 在静态存储单元中，在形成在隔离区（203）上方的有源区（202C）与栅电极结构（210A）连接的接触元件的故障率可以通过在 通过隔离沟槽（203T）的侧壁（203S），在用绝缘材料填充之前，有源区域（202C）。 注入物质可以表示P型掺杂物种类和/或用于显着改变活性区域（202C）的尖端部分的材料特性的惰性物质，

公开(公告)号：WO2011008401A1

公开(公告)日：2011-01-20

申请号：PCT/US2010/038923

申请日：2010-06-17

Applicant: GLOBALFOUNDRIES INC. ,  CARTER, Richard ,  GRAETSCH, Falk ,  TRENTZSCH, Martin ,  BEYER, Sven ,  REIMER, Berthold ,  BINDER, Robert ,  BAYAH, Boris

Inventor： CARTER, Richard ,  GRAETSCH, Falk ,  TRENTZSCH, Martin ,  BEYER, Sven ,  REIMER, Berthold ,  BINDER, Robert ,  BAYAH, Boris

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: Sophisticated gate electrode structures (235 A, 235B) for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material (212) and subsequently a common gate layer stack is deposited and subsequently patterned.

Abstract translation: 在基本上相同的结构的基础上对用于N沟道晶体管和P沟道晶体管的复杂的栅电极结构（235A，235B）进行构图，然而，可以在早期制造阶段中完成功函数调整。 为此，在将期望的功函数金属物质并入高k介电材料（212）中之后，去除扩散层和覆盖层材料，随后沉积公共栅层堆叠并随后构图。

公开(公告)号：WO2010080499A3

公开(公告)日：2010-09-02

申请号：PCT/US2009068480

申请日：2009-12-17

Applicant: GLOBALFOUNDRIES INC ,  BRANOVER ALEXANDER ,  PRENGEL HELMUT W ,  ASARO ANTHONY ,  NUSSBAUM SEBASTIAN ,  STEINMAN MAURICE B

Inventor： BRANOVER ALEXANDER ,  PRENGEL HELMUT W ,  ASARO ANTHONY ,  NUSSBAUM SEBASTIAN ,  STEINMAN MAURICE B

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method for determining an operating point of a shared resource. The method includes receiving indications of access demand to a shared resource from each of a plurality of functional units and determining a maximum access demand from among the plurality of functional units based on their respective indications. The method further includes determining a required operating point of the shared resource based on the maximum access demand, wherein the shared resource is shared by each of the plurality of functional units, comparing the required operating point to a present operating point of the shared resource, and changing to the required operating point from the present operating point if the required and present operating points are different.

Abstract translation: 一种确定共享资源的工作点的方法。 该方法包括从多个功能单元中的每一个接收对共享资源的访问请求的指示，并且基于它们各自的指示来从多个功能单元中确定最大访问需求。 该方法还包括基于最大访问需求来确定共享资源的所需操作点，其中共享资源被多个功能单元中的每一个共享，将所需操作点与共享资源的当前操作点进行比较， 如果所需和现在的操作点不同，则从当前操作点改变到所需的操作点。

公开(公告)号：WO2010080499A2

公开(公告)日：2010-07-15

申请号：PCT/US2009/068480

申请日：2009-12-17

Applicant: GLOBALFOUNDRIES INC. ,  BRANOVER, Alexander ,  PRENGEL, Helmut, W. ,  ASARO, Anthony ,  NUSSBAUM, Sebastian ,  STEINMAN, Maurice B.

Inventor： BRANOVER, Alexander ,  PRENGEL, Helmut, W. ,  ASARO, Anthony ,  NUSSBAUM, Sebastian ,  STEINMAN, Maurice B.

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method for determining an operating point of a shared resource. The method includes receiving indications of access demand to a shared resource from each of a plurality of functional units and determining a maximum access demand from among the plurality of functional units based on their respective indications. The method further includes determining a required operating point of the shared resource based on the maximum access demand, wherein the shared resource is shared by each of the plurality of functional units, comparing the required operating point to a present operating point of the shared resource, and changing to the required operating point from the present operating point if the required and present operating points are different.

Abstract translation: 一种用于确定共享资源的操作点的方法。 该方法包括从多个功能单元中的每一个接收对共享资源的访问需求的指示，并且基于它们各自的指示确定多个功能单元中的最大访问需求。 该方法还包括基于最大访问需求来确定共享资源的所需工作点，其中共享资源由多个功能单元中的每个功能单元共享，将所需的操作点与共享资源的当前工作点进行比较， 并且如果所需和当前的操作点不同，则从当前操作点改变到所需的操作点。

公开(公告)号：WO2010078074A1

公开(公告)日：2010-07-08

申请号：PCT/US2009/068673

申请日：2009-12-18

Applicant: GLOBALFOUNDRIES INC. ,  LETZ, Tobias ,  FEUSTEL, Frank

Inventor： LETZ, Tobias ,  FEUSTEL, Frank

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886

Abstract: Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/ silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.

Abstract translation: 通过局部形成铜/硅化合物，可以在金属线和通孔之间的关键区域增强半导体器件复杂金属化系统中的电迁移行为。 在一些说明性实施例中，铜/硅化合物的形成可以与用于清洁暴露的表面区域和/或改变其分子结构的其它处理组合。