Pseudo-orthogonal code generator
    15.
    发明专利
    Pseudo-orthogonal code generator 有权
    PSEUDO-ORTHOGONAL CODE GENERATOR

    公开(公告)号:JP2011101334A

    公开(公告)日:2011-05-19

    申请号:JP2009293012

    申请日:2009-12-24

    CPC classification number: H04J13/10

    Abstract: PROBLEM TO BE SOLVED: To reduce an overall size by further decreasing a gate area not only by simplifying an entire configuration but also by accelerating an operating speed.
    SOLUTION: A pseudo-orthogonal code generator includes: a serial/parallel converter for converting serial transmission data into parallel data for the unit of nine bits; a four-bit counter for repeatedly counting from 0 to 15; and a combination circuit unit for sequentially generating a pseudo-orthogonal code of 16 bits using the parallel data of nine bits and a four-bit counter value. Signal processing in the combination circuit unit is represented by a predetermined expression (0≤I≤15) of cb0(I), cb1(I), cb2(I), cb3(I), C(I) wherein C(I) is 0≤I≤15 as a pseudo-orthogonal code for the parallel data of nine bits, b0-b9 are the parallel data of nine bits, and i0-i3 are four-bit counter values binarized from the I which corresponds to an index for 16-bit pseudo-orthogonal code.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题:为了通过进一步减小栅极面积来减小总体尺寸,不仅通过简化整体构造,而且通过加速操作速度。 解码:伪正交码发生器包括:串行/并行转换器,用于将串行传输数据转换成9位的并行数据; 一个从0到15重复计数的四位计数器; 以及组合电路单元,用于使用9位的并行数据和4位计数器值顺序地生成16位的伪正交码。 cb0(I),cb1(I),cb2(I),cb3(I),C(I)的预定表达式(0≤I≤15)表示组合电路单元中的信号处理,其中C(I) 作为9比特的并行数据的伪正交码,0≤I≤15,b0-b9是9比特的并行数据,i0-i3是从对应于索引的I二值化的四比特计数值 用于16位伪正交码。 版权所有(C)2011,JPO&INPIT

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