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公开(公告)号：WO1985000453A1
公开(公告)日：1985-01-31
申请号：PCT/US1983001052
申请日：1983-07-11
Applicant: PRIME COMPUTER, INC.
Inventor： PRIME COMPUTER, INC. , JONES, Paul, R., Jr. , ARDINI, Joseph, L., Jr. , JONES, Walter, A. , PAPWORTH, David, B. , RODMAN, Paul, K. , BECKWITH, Robert, F. , CHEN, Chih-ping
IPC: G06F15/00
CPC classification number: G06F9/3889 , G06F9/3867
Abstract: In order to increase flexibility and decrease cost in a micro-code controlled environment through the use of pipeline processing, a data processing system is provided for processing a sequence of program instructions having two independent pipelines: an instruction pipeline (2, 3, 4) for reading instructions from storage and providing address data for the execution pipeline, and an execution pipeline (5, 6, 7) for referencing stored data via the addresses provided by the instruction execution, each having a plurality of serially operating stages (2, 3, 4, 5, 6, 7). Both pipelines operate synchronously under the control of a pipeline control unit (1) which initiates operation of at least one stage of the execution pipeline prior to completion of operations in the instruction pipeline, providing an operation overlap of one stage of each of the pipelines for each particular instruction. The pipeline control unit (1) can independently control the flow of instructions through the pipelines allowing conditional branching and subroutine operation.
Abstract translation: 为了通过使用流水线处理来增加微码控制环境中的灵活性并降低成本，提供了一种用于处理具有两条独立管线的程序指令序列的数据处理系统：指令流水线（2,3,4） 用于从存储器读取指令并提供用于执行流水线的地址数据，以及用于经由指令执行提供的地址引用存储的数据的执行流水线（5,6,7），每个具有多个串行操作级（2,3） ，4,5,6,7）。 两条管线在管线控制单元（1）的控制下同步运行，该管线控制单元（1）在指令流水线中完成操作之前启动执行流水线的至少一级的操作，从而为每条管线的一级操作重叠， 每个特定指令。 流水线控制单元（1）可以独立地控制通过管道的指令流，允许条件分支和子程序操作。
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公开(公告)号：WO1985002033A1
公开(公告)日：1985-05-09
申请号：PCT/US1983001741
申请日：1983-11-03
Applicant: PRIME COMPUTER, INC.
Inventor： PRIME COMPUTER, INC. , DOSHI, Mahesh , SULLIVAN, Roderick, Beebe, II , SCHULER, Donald , COOPER, Lorne
IPC: G06F01/00
CPC classification number: G06F17/5022
Abstract: A digital system simulation apparatus and method enables a user to interactively control, during simulation, both sampling (170-270) and tracing of (130-164) signals in the digital system (17) whose behavior is being simulated. The behavior of the system can be approximated better by recognizing and allowing a precise definition of element outputs even though the element inputs can include undefined variables (80-112). The apparatus (60-72) allows efficient and better utilization of system memories by providing the capability of defining multiple outputs of the circuit elements in a single instruction when those outputs all have common inputs. In addition, the efficiency and precision of system simulation is further enhanced by operating in either a four signal-level mode or a nine signal-level mode, depending upon the particular circuitry being employed (110-112).
Abstract translation: 数字系统模拟装置和方法使得用户能够在仿真期间在其模拟行为的数字系统（17）中交互地控制采样（170-270）和跟踪（130-164）信号。 通过识别和允许元素输出的精确定义，即使元素输入可以包含未定义的变量（80-112），系统的行为也可以更好地近似。 当这些输出都具有共同的输入时，设备（60-72）通过提供在单个指令中定义电路元件的多个输出的能力，可以有效和更好地利用系统存储器。 此外，取决于所使用的特定电路（110-112），通过以四信号电平模式或九信号电平模式工作来进一步提高系统仿真的效率和精度。
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公开(公告)号：AT65136T
公开(公告)日：1991-07-15
申请号：AT86300987
申请日：1986-02-13
Applicant: PRIME COMPUTER INC
Inventor： IRUKULLA SUREN , PATEL BIMAL V
Abstract: The invention relates to a range transformation method for transforming the normalized divisor in a division calculation to a range wherein the transformed value differs from one by no more than the quantity 2 . The method and apparatus generate the transform multiplier value from a first high order "q" digits of the divisor and generate an out-of-range indicator signal from at least those same digits. The thus generated multiplier value is modified in response to the out-of-range indicator signal when an out-of-range condition is indicated. The apparatus employs a read-only-memory for enabling the generation of the transform multiplier value without requiring either large table look-up storage or multiplicative functions. As a result, various division methods requiring an initial transformation to provide a divisor which approaches one in value can be efficiently implemented.
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公开(公告)号：AU611675B2
公开(公告)日：1991-06-20
申请号：AU1326588
申请日：1988-03-18
Applicant: PRIME COMPUTER INC
Inventor： ARDINI JOSEPH L JR , LEFSKY BRIAN , FARR BARBARA
IPC: G01R31/26 , G01R31/28 , G01R31/30 , G01R31/317
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公开(公告)号：DE3582506D1
公开(公告)日：1991-05-23
申请号：DE3582506
申请日：1985-02-08
Applicant: PRIME COMPUTER INC
Inventor： RODMAN PAUL K
IPC: G06F12/08 , G06F12/0817 , G06F12/0831 , G06F15/16 , G06F15/177
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Patent Agency Ranking
公开(公告)号：AU604101B2
公开(公告)日：1990-12-06
申请号：AU1329288
申请日：1988-03-18
Applicant: PRIME COMPUTER INC
Inventor： LEFSKY BRIAN , NATUSCH MARY ELLEN
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公开(公告)号：CA1212477A
公开(公告)日：1986-10-07
申请号：CA457773
申请日：1984-06-28
Applicant: PRIME COMPUTER INC
Inventor： JONES WALTER A , JONES PAUL R JR , ARDINI JOSEPH L JR
Abstract: data processing system for processing a sequence of program instructions has two independent pipelines, an instruction pipeline and an execution pipeline. Each pipeline has a plurality of serially operating stages. The instruction stages read instructions from storage and form therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. Both pipelines operate synchronously under the control of a pipeline control unit which initiates operation of at least one stage of the execution pipeline prior to completion of the instruction pipeline for a particular instruction. Thereby operation of at least one instruction stage and one execution stage of the respective pipelines overlap for each program instruction. The instruction and execution pipelines share high speed memory. The pipeline control unit can independently control the flow of instructions through the two pipelines. This is important for operation in conjunction with a microcode storage element which allows conditional branching and subroutine operation. Circuitry also detects pipeline collisions and exception conditions and delays or inhibits operation of one or more of the pipeline stages in response thereto. Under control of the pipeline control unit, one of the independent pipelines can operate while the other is halted.
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公开(公告)号：CA1212476A
公开(公告)日：1986-10-07
申请号：CA457763
申请日：1984-06-28
Applicant: PRIME COMPUTER INC
Inventor： JONES WALTER A , JONES PAUL R JR , PAPWORTH DAVID B
Abstract: A data processing system for processing a sequence of program instructions has a pipeline structure which includes an instruction pipeline and an execution pipeline. Each of the instruction and execution pipelines has a plurality of serially operating stages. The instruction pipeline reads instructions from storage and forms therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. A program instruction flow prediction apparatus and method employ a high speed flow prediction storage element for predicting redirection of program flow prior to the time when the instruction has been decoded. Circuitry is further provided for updating the storage element, correcting erroneous branch and/or non-branch predictions, and accommodating instructions occurring on even or odd boundaries of the normally read double word instruction. Circuitry is further provided for updating the program flow in a single execution cycle so that no disruption to normal instruction sequencing occurs.
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公开(公告)号：CA1305562C
公开(公告)日：1992-07-21
申请号：CA564206
申请日：1988-04-14
Applicant: PRIME COMPUTER INC
Inventor： ALLISON ROBERT , LEFSKY BRIAN
IPC: G06F12/06
Abstract: A system for controlling the addressing of a memory on a predetermined multi-megabyte decode boundary, An address shifter is coupled between CPU address lines and backplane area bussed address lines. The address shifter is controlled in accordance with the control signal determined by the memory array of a largest capacity of all memory arrays. The control signal has different states to control the address shifter to couple different address bit patterns therethrough to the backplane area address bus as a function of the selected control signal state.
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公开(公告)号：CA1296437C
公开(公告)日：1992-02-25
申请号：CA538364
申请日：1987-05-29
Applicant: PRIME COMPUTER INC
Inventor： KELLER JAMES A JR
Abstract: A method and apparatus for providing a faster graphical representation of lines to be displayed from their endpoint data either uses the natural symmetry of the line or imposes a forced symmetry upon the line to reduce the processing time required for generating each of the points representing the line. The order in which the endpoints are provided to the apparatus does not change the resulting representation. An interactive process, starting at centers of a partitioned line, incrementally determines the positions of the pixels which best, within the concept of the invention, fit the actual line being represented.
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