公开(公告)号：US09620390B2

公开(公告)日：2017-04-11

申请号：US14993714

申请日：2016-01-12

Applicant: Silex Microsystems AB

Inventor： Thorbjorn Ebefors ,  Edvard Kalvesten ,  Tomas Bauer

IPC: B81B7/00 ,  H01L23/04 ,  H01L23/498 ,  H01L23/64 ,  H01L23/66 ,  H01L21/50 ,  H01L21/683 ,  H01L23/552 ,  H01L23/58 ,  H01L21/78 ,  H01L21/768 ,  H01L23/10 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/50 ,  B81B7/007 ,  B81B2207/095 ,  B81C1/00301 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/585 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29018 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/30051 ,  H01L2224/3012 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

公开(公告)号：US09514985B2

公开(公告)日：2016-12-06

申请号：US14431002

申请日：2013-09-27

Applicant: SILEX MICROSYSTEMS AB

Inventor： Thorbjorn Ebefors ,  Henrik Knutsson

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/288 ,  H01L23/48 ,  H01L21/02

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings

Abstract translation: 在半导体衬底和衬底表面上的金属图案中制造具有高纵横比的衬底通过金属通孔的方法包括在衬底上提供半导体衬底（晶片）并沉积多晶硅。 通过蚀刻掉不需要的部分来图案化衬底表面上的多晶硅。 然后，通过无电解方法将Ni选择性地沉积在多晶硅上。 通孔穿过基底，其中孔中的壁经受与上述相同的处理。 Cu通过电镀工艺沉积在Ni上。 线宽度和间距<10μm位于晶片的两侧。

公开(公告)号：US20160172241A1

公开(公告)日：2016-06-16

申请号：US15040148

申请日：2016-02-10

Applicant: SILEX MICROSYSTEMS AB

Inventor： Thorbjorn EBEFORS ,  Henrik KNUTSSON

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/288

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings

Abstract translation: 在半导体衬底和衬底表面上的金属图案中制造具有高纵横比的衬底通过金属通孔的方法包括在衬底上提供半导体衬底（晶片）并沉积多晶硅。 通过蚀刻掉不需要的部分来图案化衬底表面上的多晶硅。 然后，Ni通过无电解方法选择性地沉积在多晶硅上。 通孔穿过基底，其中孔中的壁经受与上述相同的处理。 Cu通过电镀工艺沉积在Ni上。 线宽度和间距<10μm位于晶片的两侧。

公开(公告)号：US09240373B2

公开(公告)日：2016-01-19

申请号：US14384606

申请日：2013-03-12

Applicant: SILEX MICROSYSTEMS AB

Inventor： Thorbjörn Ebefors ,  Daniel Perttu

IPC: H01L21/66 ,  H01L23/498 ,  H01L23/14 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/525

CPC classification number: H01L23/49827 ,  H01L21/30625 ,  H01L21/308 ,  H01L21/486 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/525 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.

Abstract translation: 本发明涉及一种半导体结构，其包括具有第一侧（FS）和相对的第二侧（BS）的半导体材料的衬底。 存在至少一个包含金属的导电晶片通孔（V）和设置在衬底的第一侧和衬底的半导体材料中的至少一个凹部（RDL）。 凹槽填充有金属并与晶片通孔无缝连接。 填充通孔的金属和填充有金属的凹槽的暴露表面基本上与衬底的第一侧上的衬底表面齐平。 还提供一种包括上述结构的插入器，还包括用于将电路板和集成电路附接到插入器的相对侧上的触点。 还提供了制造该结构的方法。

公开(公告)号：US09190356B2

公开(公告)日：2015-11-17

申请号：US14384606

申请日：2013-03-12

Applicant: SILEX MICROSYSTEMS AB

Inventor： Thorbjörn Ebefors ,  Daniel Perttu

IPC: H01L21/66 ,  H01L23/498 ,  H01L23/14 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/525

Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.

公开(公告)号：US20150255344A1

公开(公告)日：2015-09-10

申请号：US14431002

申请日：2013-09-27

Applicant: SILEX MICROSYSTEMS AB

Inventor： Thorbjorn Ebefors ,  Henrik Knutsson

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings

Abstract translation: 在半导体衬底和衬底表面上的金属图案中制造具有高纵横比的衬底通过金属通孔的方法包括在衬底上提供半导体衬底（晶片）并沉积多晶硅。 衬底表面上的多晶硅通过蚀刻掉不需要的部分而被图案化。 然后，Ni通过无电解方法选择性地沉积在多晶硅上。 通孔穿过基底，其中孔中的壁经受与上述相同的处理。 Cu通过电镀工艺沉积在Ni上。 线宽度和间距<10μm位于晶片的两侧。

公开(公告)号：US20140346657A1

公开(公告)日：2014-11-27

申请号：US14365235

申请日：2012-12-17

Applicant: SILEX MICROSYSTEMS AB

Inventor： Thorbjorn Ebefors ,  Niklas Svedin

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00285 ,  B81B7/0038 ,  B81C1/00293 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.

Abstract translation: 一种用于在微电子/机械系统（MEMS）装置中密封空腔以在密封空腔内提供受控气氛的方法包括提供其上在基板的局部区域上提供模板的半导体衬底。 模板定义了腔的内部形状。 孔被制成以便能够排出空腔以提供期望的气氛以通过孔进入空腔。 最后，在孔中设置密封材料以密封空腔。 密封可以通过密封材料的压缩和/或熔化来制造。

公开(公告)号：US09511999B2

公开(公告)日：2016-12-06

申请号：US14365235

申请日：2012-12-17

Applicant: SILEX MICROSYSTEMS AB

Inventor： Thorbjorn Ebefors ,  Niklas Svedin

IPC: H01L21/76 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00285 ,  B81B7/0038 ,  B81C1/00293 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.

Abstract translation: 一种用于在微电子/机械系统（MEMS）装置中密封空腔以在密封空腔内提供受控气氛的方法包括提供其上在基板的局部区域上提供模板的半导体衬底。 模板定义了腔的内部形状。 孔被制成以便能够排出空腔以提供期望的气氛以通过孔进入空腔。 最后，在孔中设置密封材料以密封空腔。 密封可以通过密封材料的压缩和/或熔化来制造。

公开(公告)号：US09507142B2

公开(公告)日：2016-11-29

申请号：US14410211

申请日：2013-06-12

Applicant: SILEX MICROSYSTEMS AB

Inventor： Peter Agren

IPC: G02B26/08 ,  H01L23/48 ,  B81B3/00 ,  B81C1/00 ,  G01D5/24 ,  H01L23/522

CPC classification number: G02B26/0841 ,  B81B3/0021 ,  B81B3/0045 ,  B81B2201/02 ,  B81B2201/03 ,  B81B2203/04 ,  B81C1/00357 ,  B81C1/00619 ,  G01D5/24 ,  G02B26/085 ,  H01L23/481 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, includes a semiconductor substrate (10) having a first (12a) and a second (12b) side. There is provided at least one via (15) extending through the substrate (10) having first (16a) and second (16b) end surfaces, the first end surface (16a) constituting a transducer electrode for interacting with a movable element (14) arranged at the first side (12a) of the substrate (10). A shield (17) is provided on and covers at least part of the first side (12a) of the substrate (10), the shield/mask (17) including a conductive layer (19a) and an insulating material layer (19b) provided between the substrate (10) and the conductive layer (19a). The mask has an opening (18) exposing only a part of the first surface (16a) of the via. Preferably the opening (18) in the mask is precisely aligned with the movable element, and the area of the opening is accurately defined.

Abstract translation: 半导体器件包括具有第一（12a）和第二（12b）侧的半导体衬底（10）。 提供至少一个通过具有第一（16a）和第二（16b）端面的基板延伸的通孔（15），第一端面（16a）构成用于与可移动元件（14）相互作用的换能器电极， 布置在基板（10）的第一侧（12a）处。 在衬底（10）的第一侧（12a）的至少一部分上设置有屏蔽（17），所述屏蔽/掩模（17）包括导电层（19a）和绝缘材料层（19b） 在所述基板（10）和所述导电层（19a）之间。 掩模具有仅露出通孔的第一表面（16a）的一部分的开口（18）。 优选地，掩模中的开口（18）与可移动元件精确对准，并且开口的区域被精确地限定。

公开(公告)号：US20160035662A1

公开(公告)日：2016-02-04

申请号：US14881868

申请日：2015-10-13

Applicant: SILEX MICROSYSTEMS AB

Inventor： Thorbjörn EBEFORS ,  Daniel PERTTU

IPC: H01L23/498 ,  H01L21/308 ,  H01L21/48 ,  H01L21/306

CPC classification number: H01L23/49827 ,  H01L21/30625 ,  H01L21/308 ,  H01L21/486 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/525 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.