公开(公告)号：WO2007121585A1

公开(公告)日：2007-11-01

申请号：PCT/CA2007/000698

申请日：2007-04-24

Applicant: SIRIFIC WIRELESS CORPORATION ,  BELLAOUAR, Abdellatif ,  FRECHETTE, Michel, J., G., J., P.

Inventor： BELLAOUAR, Abdellatif ,  FRECHETTE, Michel, J., G., J., P.

IPC: H03F3/45 ,  H03F3/04 ,  H03G3/20 ,  H04B1/26

CPC classification number: H03G1/04 ,  H03F1/26 ,  H03F3/24 ,  H03F3/347 ,  H03F3/45071 ,  H03F2200/162 ,  H03F2200/447

Abstract: A CMOS automatic gain control (AGC) circuit that receives an analog control voltage and generates a temperature compensated gain voltage to linearly control the gain of a variable gain circuit operating in the sub-threshold region. A PTAT circuit having a resistor network coupled to a current mirror circuit operating in the sub-threshold region establishes a current having an proportional relationship to temperature. This current is used as a supply for a voltage to voltage converter circuit which generates an intermediate voltage in response to the analog control voltage. A linearizing circuit operating in the sub-threshold region pre-conditions the intermediate voltage, which is then applied to a variable gain circuit. The variable gain circuit is operated in the sub-threshold region, and the preconditioned intermediate voltage will control the amount of gain to be substantially linear with respect to the analog control voltage, and with a range of about 85dB.

Abstract translation: 一种CMOS自动增益控制（AGC）电路，其接收模拟控制电压并产生温度补偿增益电压，以线性地控制在子阈值区域中工作的可变增益电路的增益。 具有耦合到在次阈值区域中工作的电流镜电路的电阻网络的PTAT电路建立与温度成比例关系的电流。 该电流用作电压到电压转换器电路的电源，该电压对电压转换器电路响应于模拟控制电压产生中间电压。 在亚阈值区域中操作的线性化电路预先规定中间电压，然后将其施加到可变增益电路。 可变增益电路在子阈值区域中工作，预处理的中间电压将控制增益量相对于模拟控制电压基本为线性，并且范围约为85dB。

公开(公告)号：WO2007109879A1

公开(公告)日：2007-10-04

申请号：PCT/CA2007/000443

申请日：2007-03-21

Applicant: SIRIFIC WIRELESS CORPORATION ,  DOSANJH, Sathwant ,  MANKU, Tajinder ,  HOLDEN, Alan

Inventor： DOSANJH, Sathwant ,  MANKU, Tajinder ,  HOLDEN, Alan

IPC: H04B7/08 ,  H04B1/18 ,  H04Q7/32

CPC classification number: H04B1/50 ,  H04B1/0057

Abstract: A transceiver interface architecture where the same RF transceiver can be used in wireless devices that support any number of standards, with or without receive diversity implementation. Each input port of the RF transceiver can be shared by a number of input signals, which effectively expands the number of available input ports. Input port sharing can be realized with virtual ports that receive two or more input signals and selectively pass one signal to the physical input port. The use of virtual ports allows for flexible wireless design implementations using the same RF transceiver, and in particular, for receive diversity implementations that inherently require dedicated input ports. The use of low cost and small area virtual ports obviates the need for larger and more costly RF receivers.

Abstract translation: 收发器接口架构，其中相同的RF收发器可以在支持任何数量的标准的无线设备中使用，具有或不具有接收分集实现。 RF收发器的每个输入端口可以由多个输入信号共享，这有效地扩展了可用输入端口的数量。 可以通过接收两个或多个输入信号的虚拟端口实现输入端口共享，并选择性地将一个信号传递到物理输入端口。 使用虚拟端口允许使用相同RF收发器的灵活的无线设计实现，并且特别地，对于固有地需要专用输入端口的接收分集实现。 使用低成本和小面积的虚拟端口消除了对更大和更昂贵的RF接收器的需要。

公开(公告)号：WO2005112281A1

公开(公告)日：2005-11-24

申请号：PCT/CA2005/000732

申请日：2005-05-13

Applicant: SIRIFIC WIRELESS CORPORATION ,  MANKU, Tajinder ,  KAHRIZI, Masoud

Inventor： MANKU, Tajinder ,  KAHRIZI, Masoud

IPC: H04B1/26

CPC classification number: H04B1/30 ,  H03D7/00 ,  H04B15/06 ,  H04B2215/065

Abstract: A method and system for dynamically shifting spurious tones away from the desired frequency in a virtual local oscillator receiver, such that any undesired signal residing at such spurious tones are effectively delineated from the desired signal and removed from the RF input signal. The system detects the presence of potential undesired blocker signals in the RF input signal, and initiates an iterative power comparison and mixer signal adjustment loop. As the virtual local oscillator uses two mixer signals, the frequency of one of the mixer signals is adjusted during the loop until the power of the down-converted signal is minimized to a predetermined level. Minimized power in the down-converted signal is indicative of the absence of the blocker signal, since the presence of a relatively high power signal is indicative of a blocker signal overlapping with a desired signal.

Abstract translation: 一种用于在虚拟本地振荡器接收机中动态地将杂散音调从期望频率移位的方法和系统，使得驻留在这种假音调处的任何不需要的信号被有效地从期望的信号中描绘出并从RF输入信号中去除。 该系统检测RF输入信号中存在潜在的不希望的阻塞信号，并启动迭代功率比较和混频信号调节环路。 由于虚拟本地振荡器使用两个混频器信号，所以在环路中调整混频信号之一的频率，直到下变频信号的功率被最小化到预定的电平。 下变频信号中的最小化功率表示不存在阻塞信号，因为相对高功率信号的存在表示阻塞信号与期望信号重叠。

公开(公告)号：WO2005062461A1

公开(公告)日：2005-07-07

申请号：PCT/CA2004/002190

申请日：2004-12-22

Applicant: SIRIFIC WIRELESS CORPORATION ,  YAVORSKYY, Volodymyr ,  MANKU, Tajinder ,  WEI, James

Inventor： YAVORSKYY, Volodymyr ,  MANKU, Tajinder ,  WEI, James

IPC: H03B5/02

CPC classification number: H03B5/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1293 ,  H03B2200/0088 ,  H03L7/099

Abstract: A low-phase noise voltage control oscillator (VCO) comprising a voltage source for supplying control voltage to the VCO core; a phase lock loop, having an output connected to an input of the voltage source; a VCO core, including an amplifier circuit with noiseless biasing and a tank circuit with noiseless biasing of the varactors; having an output connected to an input of the phase lock loop; and an attenuator, located between the voltage source and the VCO core, for reducing phase noise from the voltage source to the VCO core.

Abstract translation: 一种低相位噪声电压控制振荡器（VCO），包括用于向VCO核心提供控制电压的电压源; 锁相环，具有连接到电压源的输入的输出; VCO核心，包括具有无噪声偏置的放大器电路和具有无阻抗偏置的变容二极管的电路; 具有连接到所述锁相环的输入的输出; 以及位于电压源和VCO核心之间的衰减器，用于减小从电压源到VCO核心的相位噪声。

公开(公告)号：WO2004036776A1

公开(公告)日：2004-04-29

申请号：PCT/CA2003/001574

申请日：2003-10-15

Applicant: SIRIFIC WIRELESS CORPORATION ,  MANKU, Tajinder

Inventor： MANKU, Tajinder

IPC: H04B1/26

CPC classification number: H04L25/061 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/161 ,  H03D2200/0043 ,  H03D2200/0047 ,  H03D2200/0084 ,  H03D2200/009 ,  H04B1/26 ,  H04L25/085

Abstract: The present invention relates generally to communications, and more specifically to a method and apparatus for minimizing DC offset and second-order modulation products (IM2 noise) while demodulating RF signals. The principle of the invention can be applied to differential, down-conversion circuits (50) consisting of two differential mixers (54, 56) in series, as follows: a pair of current sources la and Ib are used to provide current to positive and negative channels of the first differential mixer (54). Providing current to the amplifying transistors of the first mixer (54) reduces the current drawn through the active mixer switches, reducing the noise generated. The current sources la and Ib are trimmed in a complementary manner where 1a = I + Delta1, and 1b = - Delta1. The value of Δl can be determined in a number of manners; for example, it could be established by testing after the circuit has been fabricated, and the value stored on-chip, for future use.

Abstract translation: 本发明一般涉及通信，更具体地涉及一种在解调RF信号的同时最小化DC偏移和二阶调制产物（IM2噪声）的方法和装置。 本发明的原理可以应用于由串联的两个差分混频器（54,56）组成的差分，下变频电路（50），如下所示：一对电流源1a和1b用于向正和负电流提供电流， 第一差分混合器（54）的负通道。 向第一混频器（54）的放大晶体管提供电流减少了通过有源混频器开关引起的电流，从而降低了产生的噪声。 以1a = I + Delta1和1b =-Δ1的互补方式修剪电流源1a和1b。 Deltal的价值可以通过多种方式来确定; 例如，可以通过在电路制造之后进行测试，并将该值存储在芯片上，以备将来使用。

公开(公告)号：WO2008074129A1

公开(公告)日：2008-06-26

申请号：PCT/CA2007/002247

申请日：2007-12-13

Applicant: SIRIFIC WIRELESS CORPORATION ,  MANKU, Tajinder ,  SNYDER, Christopher

Inventor： MANKU, Tajinder ,  SNYDER, Christopher

IPC: H03K5/135 ,  H03L7/06 ,  H03L7/091 ,  H03L7/099

CPC classification number: H03K5/135 ,  H03L7/091 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10

Abstract: A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.

Abstract translation: 数字锁相环（PLL）电路具有数字电荷泵电路，用于提供对应于对应于压控振荡器的内部时钟和参考时钟之间的相位差的数字信号。 这些数字信号由数字处理电路处理以提供数字控制信号。 一些数字控制信号被转换成模拟控制信号，以提供压控振荡器的精确控制，而其余的数字控制信号提供压控振荡器的粗略控制。

公开(公告)号：WO2007068088A1

公开(公告)日：2007-06-21

申请号：PCT/CA2006/001983

申请日：2006-12-05

Applicant: SIRIFIC WIRELESS CORPORATION ,  BELLAOUAR, Abdellatif ,  FRIDI, Ahmed, R. ,  BALASUBRAMANIYAN, Arul, M.

Inventor： BELLAOUAR, Abdellatif ,  FRIDI, Ahmed, R. ,  BALASUBRAMANIYAN, Arul, M.

IPC: H03L7/081 ,  H04B1/40 ,  H04Q7/32

CPC classification number: H03L7/0893 ,  H03L7/099 ,  H03L2207/06

Abstract: A phase locked loop (PLL) with reduced loop filter components having dual charge pumps and corresponding dual signal paths that reduce on-chip component size within the filters. The dual paths are combined advantageously via dual varactors within a voltage controlled oscillator to further reduce loop filter components. The PLL removes the drawbacks of noise introduced by circuitry normally used for summing dual path configurations.

Abstract translation: 具有减小的环路滤波器组件的锁相环（PLL），具有双电荷泵和相应的双信号路径，其减少滤波器内的片上组件尺寸。 双路径有利地通过压控振荡器内的双变容二极管组合以进一步减少环路滤波器部件。 PLL消除了通常用于求和双路径配置的电路引入的噪声的缺点。

公开(公告)号：WO2007065270A1

公开(公告)日：2007-06-14

申请号：PCT/CA2006/002004

申请日：2006-12-11

Applicant: SIRIFIC WIRELESS CORPORATION ,  HOLDEN, Alan, R. ,  JAEHNIG, Jason, P.

Inventor： HOLDEN, Alan, R. ,  JAEHNIG, Jason, P.

IPC: H04B1/40 ,  H04B1/30 ,  H04B1/26

CPC classification number: H04B1/005 ,  H03D7/14

Abstract: A wideband mixer circuit that is flexible and reconfigurable so that several identical wideband mixer circuits may be used in lieu of several fixed narrow-band mixers. Such wideband mixer circuits can be provided in multiples within a chip such that multiple inputs are each within a wide frequency range (i.e., 3 GHz) and may be actively narrowed to any desired frequency range by way of the operation inherent to the circuit architecture. Such a chip supports multiple standards at each input.

Abstract translation: 一种宽带混频器电路，其灵活和可重新配置，使得可以使用几个相同的宽带混频器电路来代替几个固定的窄带混频器。 这样的宽带混频器电路可以在芯片内以多个倍数提供，使得多个输入各自处于宽的频率范围（即3GHz）内，并且可以通过电路架构固有的操作而被主动变窄到任何期望的频率范围。 这样的芯片在每个输入端都支持多种标准。

公开(公告)号：WO2007065269A1

公开(公告)日：2007-06-14

申请号：PCT/CA2006/002003

申请日：2006-12-11

Applicant: SIRIFIC WIRELESS CORPORATION ,  HOLDEN, Alan, R.

Inventor： HOLDEN, Alan, R.

IPC: H03M1/12 ,  H03H17/00 ,  H03M1/18 ,  H03M3/02 ,  H04B1/16 ,  H04Q7/32

CPC classification number: H04B1/30 ,  H04B1/0028 ,  H04B1/0032

Abstract: A CMOS hybrid analog-digital receiver core where filtering and gain functions are implemented in the digital domain. The analog portion of the receiver core includes standard circuits such as a low noise amplifier for receiving an RF input signal, and a mixer circuit for down-converting the RF input signal to a base band frequency signal. The analog to digital conversion function is provided by a merged ADC filter circuit having a low order filter stage and an ADC stage. The low order filter stage performs low order filtering of the base band signal to reduce dynamic range and clock requirements for subsequent analog to digital conversion the ADC stage. The two circuit stages are considered to be merged since they both consist of an interconnection of identical transconductance cells, where each transconductance cell includes a series of interconnected CMOS inverters.

Abstract translation: CMOS数字接收机芯片，其中滤波和增益功能在数字领域得以实现。 接收机核心的模拟部分包括标准电路，例如用于接收RF输入信号的低噪声放大器，以及用于将RF输入信号下变频为基带频率信号的混频电路。 模数转换功能由具有低阶滤波级和ADC级的合并ADC滤波电路提供。 低阶滤波器级对基带信号进行低阶滤波，以减少ADC级的后续模数转换的动态范围和时钟要求。 两个电路级被认为是合并的，因为它们都由相同跨导单元的互连构成，其中每个跨导单元包括一系列互连的CMOS反相器。

公开(公告)号：WO2004010576A1

公开(公告)日：2004-01-29

申请号：PCT/CA2003/001066

申请日：2003-07-24

Applicant: SIRIFIC WIRELESS CORPORATION ,  KHAJEHPOUR, Javad

Inventor： KHAJEHPOUR, Javad

IPC: H03F3/72

CPC classification number: H03F1/565 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/429 ,  H03F2200/451 ,  H03F2203/45371 ,  H03F2203/45386 ,  H03F2203/45481 ,  H03F2203/45616 ,  H03F2203/45704 ,  H03F2203/45726 ,  H03F2203/7239 ,  H03J2200/10

Abstract: The present invention relates generally to amplifiers, and more specifically to multi-band and/or multi-standard low noise amplifiers. There are currently no inexpensive, high­performance, fully-integrable, multi-standard low noise amplifiers (LNAs) available. The invention provides a suitable LNA for a multi-band and/or multi-standard receiver in wireless and other applications. This LNA comprises a positive signal amplifier having a first input for receiving a positive RF signal, and a first output for providing an amplified positive RF signal; a negative signal amplifier having a second input for receiving a negative RF signal, and a second output for providing an amplified negative RF signal; and a tunable differential filter having a tuning control input, a third input for said first output and a fourth input for said second output; the frequency response of said tunable differential filter varying with a control signal input to said tuning control input, whereby signal of undesired frequencies may be filtered from said first output and said second output.

Abstract translation: 本发明一般涉及放大器，并且更具体地涉及多频带和/或多标准低噪声放大器。 目前还没有廉价，高性能和可怕的;性能可完全集成的多标准低噪声放大器（LNA）。 本发明为无线和其他应用中的多频带和/或多标准接收机提供合适的LNA。 该LNA包括具有用于接收正RF信号的第一输入和用于提供放大的正RF信号的第一输出的正信号放大器; 负信号放大器，具有用于接收负RF信号的第二输入和用于提供放大的负RF信号的第二输出; 以及可调差分滤波器，其具有调谐控制输入，用于所述第一输出的第三输入和用于所述第二输出的第四输入; 所述可调差分滤波器的频率响应随着输入到所述调谐控制输入的控制信号而变化，由此可以从所述第一输出和所述第二输出中滤除不期望频率的信号。