公开(公告)号：WO2009047588A1

公开(公告)日：2009-04-16

申请号：PCT/IB2007/055367

申请日：2007-10-09

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ST MICROELECTRONICS (Crolles 2) SAS ,  LAGHA, Anissa ,  FOX, Robert ,  BROUSSOUS, Lucile ,  LEVY, Didier

Inventor： LAGHA, Anissa ,  FOX, Robert ,  BROUSSOUS, Lucile ,  LEVY, Didier

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/02063 ,  H01L21/76811

Abstract: A method for manufacturing a semiconductor device includes providing a patterned hard- mask layer (41). The hard-mask layer (41) is provided on an exposed surface (16) of one or more layers to be patterned of a semiconductor intermediate product (1). The hard-mask layer (41) covers the exposed surface (16) in covered areas (46) of the one or more layers to be patterned and does not cover the exposed surface (16) in bared areas (47) of the one or more layers to be patterned. One or more recesses (17,48,50) are formed in the layers to be patterned by at least partially removing the layers to be patterned in the bared areas (47). The hard-mask layer (41) is ten removed. After removing the hard-mask layer (41) the recess (17,48,50) is filled with a filling material (31,32).

Abstract translation: 一种制造半导体器件的方法包括提供图案化的硬掩模层（41）。 硬掩模层（41）设置在待图形化的半导体中间产品（1）的一层或多层的暴露表面（16）上。 硬掩模层（41）覆盖待图案化的一个或多个层的覆盖区域（46）中的暴露表面（16），并且不覆盖暴露表面（16）在裸露区域（47）中的暴露表面（16） 更多层被图案化。 通过至少部分地去除在裸露区域（47）中待图案化的层，在待图案化的层中形成一个或多个凹槽（17,48,50）。 去除硬掩模层（41）。 在去除硬掩模层（41）之后，凹部（17,48,50）填充有填充材料（31,32）。

公开(公告)号：WO2008110497A1

公开(公告)日：2008-09-18

申请号：PCT/EP2008/052731

申请日：2008-03-06

Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  MULLER, Markus Gerhard Andreas ,  CORONEL, Philippe

Inventor： MULLER, Markus Gerhard Andreas ,  CORONEL, Philippe

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/6681 ,  H01L29/7855

Abstract: A FinFET (100) comprises a fin-shaped layer-section (116) of a single-crystalline active semiconductor layer (104) extending on an insulating substrate layer (106) along a longitudinal fin direction between, a source layer-section (122), and a drain layer-section (124) of the single-crystalline active semiconductor layer (104). Furthermore, two separate gate-electrode layers (138.1, 138.2) are provided, which do not form sections of the single- crystalline active semiconductor layer, each of the gate-electrode layers facing one of the opposite side faces of the fin- shaped layer-section (116). Each gate-electrode layer is connected with a respective separate gate contact (154, 156). The gate-electrode layers, as seen in a cross-sectional view of a plane that is perpendicular to the longitudinal fin- direction, are arranged on the substrate layer (106) between the respective side face of the fin-shaped layer section and a respective contact-post layer section (118, 120) of the single- crystalline semiconductor layer (104).

Abstract translation: FinFET（100）包括沿着纵向翅片方向在绝缘衬底层（106）上延伸的源极层部分（122）的单晶有源半导体层（104）的鳍状层部分（116） ）和单晶有源半导体层（104）的漏极层（124）。 此外，提供两个单独的栅极电极层（138.1,138.2），其不形成单晶有源半导体层的部分，每个栅极电极层面对鳍状层的相对侧面之一 （116）。 每个栅极电极层与相应的单独的栅极触点（154,156）连接。 如垂直于纵向翅片方向的平面的截面图所示，栅极电极层被布置在鳍状层部分的相应侧面之间的基底层（106）和 单晶半导体层（104）的相应接触柱层部分（118,120）。

公开(公告)号：WO2008028851A1

公开(公告)日：2008-03-13

申请号：PCT/EP2007/058999

申请日：2007-08-29

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  GOSSET, Laurent ,  TORRES, Joaquin

Inventor： GOSSET, Laurent ,  TORRES, Joaquin

IPC: H01L29/06 ,  H01L21/768

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/76831 ,  H01L21/76879 ,  H01L29/0673 ,  H01L29/0676 ,  H01L2221/1094

Abstract: An interconnect structure on a substrate is provided. The interconnect structure comprises electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level. In the interconnect structure of the invention, at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level. The via extends in a via opening of a first dielectric layer and comprises an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures. At least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture that is small enough to prevent a penetration of the carbon nanostructures through the via aperture. This structure enhances control of carbon nanostructure growth in a height direction during fabrication of the interconnect structure.

Abstract translation: 提供了衬底上的互连结构。 互连结构包括在衬底层上或上方的至少两个互连层上的导电互连元件。 在本发明的互连结构中，至少一个导电通孔将一个互连层上的第一互连元件或衬底层上的第一互连元件连接到不同互连层上的第二互连元件。 通孔在第一电介质层的通孔中延伸，并且包括含有导电圆柱形碳纳米结构的导电通孔材料。 至少一个覆盖层段到达通孔开口的横向延伸部分，并限定通孔孔，其足够小以防止碳纳米结构穿过通孔。 该结构在互连结构的制造期间增强了在高度方向上碳纳米结构生长的控制。

公开(公告)号：WO2009081345A1

公开(公告)日：2009-07-02

申请号：PCT/IB2008/055418

申请日：2008-12-18

Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  POUYDEBASQUE, Arnaud ,  CORONEL, Philippe ,  DENORME, Stephane

Inventor： POUYDEBASQUE, Arnaud ,  CORONEL, Philippe ,  DENORME, Stephane

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66772 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/66636 ,  H01L29/7831 ,  H01L29/78654

Abstract: The present invention relates to a method for fabricating a planar independent- double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

Abstract translation: 本发明涉及在体半导体衬底上制造平面独立双栅极FET或平面栅极全周围FET的方法。 该方法包括在有源半导体区域中用掩埋牺牲层重新填充表面凹槽，并且在通过相应的沉积和图案化准备预处理栅极堆叠之后，在隔离区域中形成凹槽，以便使凹部 在指向内衬底的深度方向上延伸到允许去除掩埋牺牲层的深度水平，并且使得凹槽在通道方向上削弱栅极堆叠的部分。

公开(公告)号：WO2007107176A1

公开(公告)日：2007-09-27

申请号：PCT/EP2006/004034

申请日：2006-03-17

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  COOPER, Kevin ,  KORDIC, Srdjan ,  RIVOIRE, Maurice

Inventor： COOPER, Kevin ,  KORDIC, Srdjan ,  RIVOIRE, Maurice

IPC: H01L21/3105 ,  B24B37/04 ,  B24D17/00 ,  H01L21/304

CPC classification number: H01L21/3105 ,  B24B9/065 ,  B24B37/042 ,  H01L21/304

Abstract: A method of minimizing de lamination of a layer (14, 16, or 18), the method includes providing a semiconductor substrate (12), forming a first layer (14) over the semiconductor substrate, wherein the first layer has a first corner (20) and the first corner has a first angle of approximately 90 degrees; forming a second layer (16) over the first layer, wherein the second layer has a second corner (20) and the second corner has a second angle of approximately 90 degrees, and modifying the first and second corners to form a first slanted edge (50, 60, or 70) of the first layer and a second slanted edge (50, 60, or 70) of the second layer, wherein the first slanted edge and the second slanted edge are continuous with each other and the first slanted edge forms a third angle with respect to the semiconductor substrate, wherein the third angle is less than 30 degrees.

Abstract translation: 一种使层（14,16或18）的层叠最小化的方法，所述方法包括提供半导体衬底（12），在所述半导体衬底上形成第一层（14），其中所述第一层具有第一角（ 20），并且第一角具有大约90度的第一角度; 在所述第一层上形成第二层（16），其中所述第二层具有第二角（20），并且所述第二角具有大约90度的第二角度，并且修改所述第一和第二角以形成第一倾斜边缘 50,60或70）和所述第二层的第二倾斜边缘（50,60或70），其中所述第一倾斜边缘和所述第二倾斜边缘彼此连续并且所述第一倾斜边缘形成 相对于半导体衬底的第三角度，其中第三角度小于30度。

公开(公告)号：WO2008065125A1

公开(公告)日：2008-06-05

申请号：PCT/EP2007/062905

申请日：2007-11-27

Applicant: NXP B.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  TORRES, Joaquin ,  GOSSET, Laurent ,  ARNAL, Vincent ,  CHHUN, Sonarith

Inventor： TORRES, Joaquin ,  GOSSET, Laurent ,  ARNAL, Vincent ,  CHHUN, Sonarith

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a self-aligned diffusion-barrier cap on a Cu- containing conductive element in an integrated-circuit device comprises: - providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface; - depositing a metal layer on the exposed surface of conductive element; - inducing diffusion of metal from the metal layer into a top section of the conductive element; - removing the remaining metal layer; - letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.

Abstract translation: 一种用于在集成电路器件中的含Cu导电元件上制造自对准扩散阻挡帽的方法包括： - 提供具有横向插入电介质层并具有暴露表面的含Cu导电元件的衬底; - 在导电元件的暴露表面上沉积金属层; - 诱导金属从金属层扩散到导电元件的顶部; - 去除剩余的金属层; - 使导电元件的顶部中的扩散金属和第二组分的颗粒彼此反应，以便构成覆盖导电元件的化合物。 选择金属层和第二组分的金属，使得该化合物形成抵抗Cu扩散的扩散阻挡层。 实现了集成电路器件的互连叠层中介电材料的介电常数的降低。

公开(公告)号：WO2008028850A1

公开(公告)日：2008-03-13

申请号：PCT/EP2007/058998

申请日：2007-08-29

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  JOURDAN, Nicolas ,  GOSSET, Laurant Georges ,  TORRES, Joaquin

Inventor： JOURDAN, Nicolas ,  GOSSET, Laurant Georges ,  TORRES, Joaquin

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the Copper-containing feature to the dielectric layer, a CuSiN layer and a SiN layer. This layer combinat ion provides an efficient barrier for suppressing Copper diffusion from the feature into the dielectric layer. Furthermore, a CuSiN/SiN layer sequence provides an improved adhesion between the layers of the diffusion-barrier layer stack and the dielectric layer, and thus improves the electromigration performance of the integrated-circuit device during operation. Therefore, the reliability of device operation and the lifetime of the integrate- circuit device are improved in comparison with prior-art devices. The invention further relates to a method for fabricating such an integrated-circuit device.

Abstract translation: 本发明涉及在电介质层中具有至少一个含铜特征的集成电路器件，以及布置在该特征与该介电层之间的扩散阻挡层堆叠。 本发明的集成电路器件具有扩散阻挡层堆叠，其包括在从含铜特征到电介质层的方向上具有CuSiN层和SiN层。 该层组合离子提供了有效的屏障，用于抑制从特征进入电介质层的铜扩散。 此外，CuSiN / SiN层序列提供了扩散阻挡层堆叠层和电介质层之间的改进的粘合性，从而提高了集成电路器件在操作期间的电迁移性能。 因此，与现有技术的器件相比，器件操作的可靠性和集成电路器件的寿命得到改善。 本发明还涉及一种用于制造这种集成电路器件的方法。

公开(公告)号：WO2008015212A1

公开(公告)日：2008-02-07

申请号：PCT/EP2007/057899

申请日：2007-07-31

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  BROEKAART, Marcel, Eduard, Irene ,  DE-JONGHE, Veronique ,  LEVERD, François

Inventor： BROEKAART, Marcel, Eduard, Irene ,  DE-JONGHE, Veronique ,  LEVERD, François

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

Abstract: The present invention relates to a method for fabricating at least one feature, which has a target lateral width, in a substrate layer. The method allows fabricating a feature with a target lateral width in a substrate layer that is smaller than can be obtained with the used lithographic equipment. In comparison with known methods, it provides an increased resistance to temperatures typically used during processing, in particular, during a plasma etching step. The increased temperature resistance is achieved by using a layer structure that comprises an amorphous carbon layer on the substrate layer, a capping layer on the amorphous carbon layer, and a first resist layer structure on the capping layer. In this layer structure, a carbon contribution to the etching process, which is usually provided by a resist material, is provided by the amorphous carbon layer, which forms a hard mask on the substrate layer.

Abstract translation: 本发明涉及在衬底层中制造具有目标横向宽度的至少一个特征的方法。 该方法允许制造在衬底层中具有小于可以使用所使用的光刻设备获得的目标横向宽度的特征。 与已知的方法相比，它提供了对加工期间通常使用的温度的增加的抗性，特别是在等离子体蚀刻步骤期间。 通过使用在基底层上包含无定形碳层，无定形碳层上的覆盖层和覆盖层上的第一抗蚀剂层结构的层结构来实现提高的耐温性。 在该层结构中，通常由抗蚀剂材料提供的对蚀刻工艺的碳贡献由在基底层上形成硬掩模的无定形碳层提供。

公开(公告)号：WO2008015211A1

公开(公告)日：2008-02-07

申请号：PCT/EP2007/057898

申请日：2007-07-31

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  MONDOT, Alexandre ,  MULLER, Markus Gerhard Andreas ,  KORMANN, Thomas

Inventor： MONDOT, Alexandre ,  MULLER, Markus Gerhard Andreas ,  KORMANN, Thomas

IPC: H01L21/20

CPC classification number: H01L21/823814 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823828 ,  H01L27/0922 ,  H01L29/4933 ,  H01L29/4975

Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behaviour according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800 °C, a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract translation: 本发明涉及用于在Si或SiGe表面上选择性沉积Si或SiGe的方法。 该方法根据第一和第二表面区域的掺杂差异，利用物理化学表面行为的差异。 通过提供具有适当浓度范围的硼掺杂的至少一个第一表面区域并且在低于或等于800℃的温度下在预烘烤步骤中将衬底表面暴露于清洁和钝化环境气氛中，随后的沉积步骤 或SiGe不会导致第一表面区域中的层沉积。 该效应用于在不掺杂硼的合适浓度范围内或掺杂有另一种掺杂剂的第二表面区域中选择性沉积Si或SiGe，或不掺杂。 因此，该方法节省了根据现有技术在第二表面区域中选择性沉积Si或SiGe所需的常规光刻序列。

公开(公告)号：WO2007088182A1

公开(公告)日：2007-08-09

申请号：PCT/EP2007/050965

申请日：2007-02-01

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ST MICROELECTRONICS (CROLLES 2) SAS ,  FREESCALE SEMICONDUCTOR, INC. ,  DUBREUIL, Olivier ,  KORDIC, Srdjan ,  CARAMBERIS, Theodore

Inventor： DUBREUIL, Olivier ,  KORDIC, Srdjan ,  CARAMBERIS, Theodore

IPC: H01L21/00

CPC classification number: H01L21/6708

Abstract: The present invention relates to a cost saving liquid-treatment unit (100). According to the invention, a control unit (152), which is connected to an input port of a control valve (118, 120, 122), is adapted to set, in dependence on the evaporation rate of a treatment liquid on the substrate at the given or desired temperature of the substrate and/or at the given or desired pressure of a gaseous ambient atmosphere at the substrate, a number of dispense pulses to be applied to the substrate for the liquid treatment, a respective pulse duration of individual dispense pulses, and respective dispense-interruption time spans between the individual dispense pulses. This way, the use of treatment liquid is reduced to a minimum amount, thus reducing costs for providing and cleaning treatment liquid.

Abstract translation: 本发明涉及节约成本的液体处理单元（100）。 根据本发明，连接到控制阀（118,120,122）的输入端口的控制单元（152）适于根据基板上处理液体的蒸发速率来设定 衬底的给定或期望温度和/或在衬底上的气体环境气氛的给定或期望压力下，要施加到用于液体处理的衬底的多个分配脉冲，各个分配脉冲的相应脉冲持续时间 ，以及各个分配脉冲之间的分配中断时间跨度。 这样，将处理液的使用降低到最小量，从而降低提供和清洁处理液体的成本。