公开(公告)号：US06384833B1

公开(公告)日：2002-05-07

申请号：US09371395

申请日：1999-08-10

Applicant: Monty Montague Denneau ,  Peter Heiner Hochschild ,  Henry Stanley Warren, Jr.

Inventor： Monty Montague Denneau ,  Peter Heiner Hochschild ,  Henry Stanley Warren, Jr.

IPC: G06T1500

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T2210/52

Abstract: The geometric processing of an ordered sequence of graphics commands is distributed over a set of processors by the following steps. The sequence of graphics commands is partitioned into an ordered set of N subsequences S0 . . . SN−1, and an ordered set of N state vectors V0 . . . VN−1 is associated with said ordered set of subsequences S0 . . . SN−1. A first phase of processing is performed on the set of processors whereby, for each given subsequence Sj in the set of subsequences S0 . . . SN−2, state vector Vj+1 is updated to represent state as if the graphics commands in subsequence Sj had been executed in sequential order. A second phase of the processing is performed whereby the components of each given state vector Vk in the set of state vectors V1 . . . VN−1 generated in the first phase is merged with corresponding components in the preceding state vectors V0 . . . Vk−1 such that the state vector Vk represents state as if the graphics commands in subsequences S0 . . . Sk−1 had been executed in sequential order. Finally, a third phase of processing is performed on the set of processors whereby, for each subsequence Sm in the set of subsequences S1 . . . SN−1, geometry operations for subsequence Sm are performed using the state vector Vm generated in the second phase. In addition, in the third phase, geometry operations for subsequence S0 are performed using the state vector V0. Advantageously, the present invention provides a mechanism that allows a large number of processors to work in parallel on the geometry operations of the three-dimensional rendering pipeline. Moreover, this high degree of parallelism is achieved with very little synchronization (one processor waiting from another) required, which results in increased performance over prior art graphics processing techniques.

Abstract translation: 图形命令的有序序列的几何处理通过以下步骤分布在一组处理器上。 图形命令的顺序被划分成N个子序列S0的有序集合。 。 。 SN-1和N个状态向量V0的有序集合。 。 。 VN-1与所述有序的子序列S0相关联。 。 。 SN-1。 对该组处理器执行第一阶段的处理，其中对于子集序列S0中的每个给定子序列Sj。 。 。 SN-2，状态向量Vj + 1被更新以表示状态，好像子序列Sj中的图形命令已按顺序执行。 执行处理的第二阶段，由此在状态向量集合V1中的每个给定状态向量V k的分量被执行。 。 。 在第一阶段生成的VN-1与先前状态矢量V0中的相应分量合并。 。 。 Vk-1，使得状态向量Vk表示如同在子序列S0中的图形命令的状态。 。 。 Sk-1已按顺序执行。 最后，对该组处理器执行第三阶段处理，其中对于子集序列S1中的每个子序列Sm。 。 。 SN-1，使用在第二阶段中生成的状态矢量Vm来执行子序列Sm的几何运算。 此外，在第三阶段中，使用状态向量V0执行子序列S0的几何运算。 有利的是，本发明提供了允许大量处理器在三维渲染流水线的几何运算上并行工作的机制。 此外，通过所需的非常少的同步（一个处理器从另一个处理器等待）来实现这种高度的并行性，这导致比现有技术的图形处理技术更高的性能。

公开(公告)号：US08016859B2

公开(公告)日：2011-09-13

申请号：US11356642

申请日：2006-02-17

Applicant: William T. Donofrio ,  Jeffrey H. Nycz ,  Steven Tethrake ,  Stanley Warren Olson, Jr.

Inventor： William T. Donofrio ,  Jeffrey H. Nycz ,  Steven Tethrake ,  Stanley Warren Olson, Jr.

IPC: A61B17/70

CPC classification number: A61B8/4472 ,  A61B5/0031 ,  A61B5/076 ,  A61B5/4509 ,  A61B5/4514 ,  A61B5/4528 ,  A61B8/0875 ,  A61B8/4281 ,  A61B8/56 ,  A61B8/565

Abstract: A system and method are provided for monitoring the condition of the skeletal system and adjusting a treatment device to provide appropriate treatment in response to the sensed signal. More particularly, in one aspect the present invention is directed to a sensor for detecting changes at a spinal level and a dynamic treatment system adjustable in response to the detected changes.

Abstract translation: 提供了一种系统和方法，用于监测骨骼系统的状况并调整治疗装置以响应于所感测的信号提供适当的治疗。 更具体地，在一个方面，本发明涉及一种用于检测脊髓水平上的变化的传感器和响应于检测到的变化而可调节的动态治疗系统。

公开(公告)号：US20080228072A1

公开(公告)日：2008-09-18

申请号：US11687574

申请日：2007-03-16

Applicant: Jeffrey H. Nycz ,  Carlos E. Gil ,  William T. Donofrio ,  Stanley Warren Olson ,  Jeetendra Bharadwaj

Inventor： Jeffrey H. Nycz ,  Carlos E. Gil ,  William T. Donofrio ,  Stanley Warren Olson ,  Jeetendra Bharadwaj

IPC: A61B8/00 ,  A61B17/00 ,  A61B17/08 ,  A61B5/05

CPC classification number: A61B5/05 ,  A61B5/4509 ,  A61B8/0833 ,  A61B8/4455 ,  A61B8/4472 ,  A61B8/56

Abstract: A surgical instrument for the presence and/or location of a foreign body is disclosed. The surgical instrument is hand-held. In some embodiments, the surgical instrument includes transducers adapted for emitting and/or receiving signals. In such embodiments, the surgical instrument utilizes pulse-echo measurements to determine characteristics and/or location of the foreign body. In other embodiments, the surgical instrument includes a measurement circuit for detecting the presence and/or location of a foreign body by a change in the characteristics of the measurement circuit. The surgical instrument may be utilized to determine such things as the size of a foreign body, the orientation of a foreign body with respect to patient anatomy and/or another foreign body, and whether the foreign body has been completely removed.

Abstract translation: 公开了一种用于异物的存在和/或位置的外科器械。 手术器械是手持式的。 在一些实施例中，外科器械包括适于发射和/或接收信号的换能器。 在这样的实施例中，手术器械利用脉冲回波测量来确定异物的特征和/或位置。 在其他实施例中，手术器械包括用于通过测量电路的特性的变化来检测异物的存在和/或位置的测量电路。 外科器械可用于确定异物的尺寸，异物相对于患者解剖结构和/或另一异物的取向以及异物是否已被完全移除。

公开(公告)号：US07203790B2

公开(公告)日：2007-04-10

申请号：US11197899

申请日：2005-08-05

Applicant: Monty Montague Denneau ,  Peter Heiner Hochschild ,  Henry Stanley Warren, Jr.

Inventor： Monty Montague Denneau ,  Peter Heiner Hochschild ,  Henry Stanley Warren, Jr.

IPC: G06F12/00

CPC classification number: G06F12/0813 ,  G06F2212/601

Abstract: Caches are associated with processors, such multiple caches may be associated with multiple processors. This association may be different for different main memory address ranges. The techniques of the invention are flexible, as a system designer can choose how the caches are associated with processors and main memory banks, and the association between caches, processors, and main memory banks may be changed while the multiprocessor system is operating. Cache coherence may or may not be maintained. An effective address in an illustrative embodiment comprises an interest group and an associated address. The interest group is an index into a cache vector table and an entry into the cache vector table and the associated address is used to select one of the caches. This selection can be pseudo-random. Alternatively, in some applications, the cache vector table may be eliminated, with the interest group directly encoding the subset of caches to use.

Abstract translation: 高速缓存与处理器相关联，这样的多个高速缓存可以与多个处理器相关联。 对于不同的主存储器地址范围，该关联可能不同。 本发明的技术是灵活的，因为系统设计者可以选择高速缓存如何与处理器和主存储器组相关联，并且高速缓存，处理器和主存储器组之间的关联可以在多处理器系统运行时改变。 缓存一致性可能维持也可能不会保持。 说明性实施例中的有效地址包括兴趣组和相关联的地址。 兴趣组是到缓存向量表的索引，并且入口到缓存向量表中，并且相关联的地址用于选择其中一个高速缓存。 该选择可以是伪随机的。 或者，在一些应用中，缓存向量表可以被消除，兴趣组直接编码要使用的高速缓存的子集。