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11.发明专利
公开(公告)号：JP2004234659A
公开(公告)日：2004-08-19
申请号：JP2004019256
申请日：2004-01-28
Applicant: Schlumberger Malco Inc , Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc , シュルンベルジェ マルコ, インコーポレイテッドSchlumberger Malco, Inc.
Inventor： LEYDIER ROBERT ANTOINE , POMET CHRISTOPHE ALAIN
CPC classification number: G06F1/04
Abstract: PROBLEM TO BE SOLVED: To generate a reference clock by using a downstream reception USB signal transmitted by a host computer or a hub. SOLUTION: A USB device having a free-running oscillator generates a local clock signal in response to a signal on a universal serial bus (USB). The oscillator is substantially stable and operates at a frequency known for substantial incorrectness. A single end bit serial signal is extracted from a reception signal transmitted by a USB host computer or a hub, and a timing signal is activated by responding to it. A bit pattern is detected and intervals are measured in the single end bit serial signal, and the timing signal is activated in that period. A period P of the local clock signal is adjusted in response to one of the measured intervals. COPYRIGHT: (C)2004,JPO&NCIPI
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12.发明专利
公开(公告)号：JP2004171573A
公开(公告)日：2004-06-17
申请号：JP2003389690
申请日：2003-11-19
Inventor： PARTHASARATHY SIVAGNANAM , DRIKER ALEXANDER
CPC classification number: G06F9/3885 , G06F9/30043 , G06F9/30072
Abstract: PROBLEM TO BE SOLVED: To provide an improved technique for extending or alternating a processor instruction set architecture. SOLUTION: The processor architecture uses a split-instruction transaction so as to supply an extension unit with an operand and an instruction and to retrieve results from the extension unit and supports an electrical interface for coupling a processor core to one or more than one coprocessor extension units executing a computational instruction. The generic instructions for sending an operation and data to the extension unit and/or retrieving data from the extension unit allow a new computational instruction to be introduced without regeneration of the processor architecture. Support for a plurality of extension units and/or a plurality of execution pipes within each extension unit, multi-cycle execution latencies and different execution latencies between or within the extension units, extension instruction predicates, and for handling result save/restore on the processor core install and the interrupt is included. COPYRIGHT: (C)2004,JPO
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公开(公告)号：JP2004165663A
公开(公告)日：2004-06-10
申请号：JP2003380089
申请日：2003-11-10
Inventor： ZHOU TIAO
IPC: G06K19/077 , G06K9/00 , H01L21/58 , H01L23/58 , H01L25/065 , H01L25/07 , H01L25/18
CPC classification number: G06K9/0002 , H01L23/573 , H01L24/48 , H01L24/83 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/73265 , H01L2224/83192 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , Y10T29/49128 , Y10T29/4913 , Y10T29/49146 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide an improved packaging technique for integrated circuits. SOLUTION: The device comprises a substrate 102, which is equipped with first integrated circuits 104, 106 and components for electronic circuit 108, 110, a first sealing structure 114 for sealing the first integrated circuits, a second integrated circuit 120 attached to the first sealing formation, and a second sealing structure 122 which seals at least a part of the first sealing formation, the first integrated circuits and a electronic component 112. COPYRIGHT: (C)2004,JPO
Abstract translation: 要解决的问题：为集成电路提供改进的封装技术。 解决方案：该装置包括衬底102，衬底102配备有第一集成电路104,106和用于电子电路108,110的部件，用于密封第一集成电路的第一密封结构114，连接到第一集成电路120的第二集成电路120 第一密封结构，以及密封第一密封结构，第一集成电路和电子部件112的至少一部分的第二密封结构122.权利要求（C）2004，JPO
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公开(公告)号：JP2004164622A
公开(公告)日：2004-06-10
申请号：JP2003354533
申请日：2003-10-15
Inventor： PARTHASARATHY SIVAGNANAM , COFLER ANDREW , CHAVEROT LIONEL
CPC classification number: G06F9/381 , G06F9/30181 , G06F9/325 , G06F9/3875 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , Y02D10/13
Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of cache access in a processor without substantially degrading performance.
SOLUTION: For instruction clusters for which no significant performance penalty such as execution of hardware loops is incurred, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, in the case that instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for remaining iterations of the hardware loop to further reduce power consumption.
COPYRIGHT: (C)2004,JPO-
公开(公告)号：JP2004125791A
公开(公告)日：2004-04-22
申请号：JP2003334020
申请日：2003-09-25
Inventor： DANIEL A THOMAS , DEBEURRE BRUNO J , THOMA PETER J
IPC: G01B7/28 , G01N27/414 , G01N33/487 , G06K9/00 , G06T1/00 , H01L51/05 , H01L51/00
CPC classification number: G01L1/146 , G01L1/148 , G01N27/4145 , G01N27/4148 , G06K9/0002 , H01L27/307 , H01L51/0508
Abstract: PROBLEM TO BE SOLVED: To provide a sensor device manufactured using an organic semiconductor material. SOLUTION: Sensor cells are arranged in the form of an array within an organic semiconductor layer. A row and column selection circuit addresses one cell of the array at a time to determine the presence of an object contacting or located in proximity to a detection surface above each cell, e.g., the protruding or recessed part of a fingerprint. A control circuit can be provided inside either a companion silicon chip or a second layer made from an organic semiconductor material in order to communicate with the array and an associated system processor. The array consisting of the sensor cells can be manufactured using a flexible polymer substrate. The substrate is peeled and disposed of after contacts are patterned on the organic semiconductor layer. The organic semiconductor layer is usable together with a reactive interface layer which is made redundant to detect a specific chemical material in a test medium. COPYRIGHT: (C)2004,JPO
Abstract translation: 要解决的问题：提供使用有机半导体材料制造的传感器装置。 传感器单元以有机半导体层内的阵列的形式排列。 行和列选择电路一次寻址阵列的一个单元，以确定接触或位于每个单元上方的检测表面附近的物体的存在，例如指纹的突出或凹入部分。 控制电路可以设置在伴随硅芯片或由有机半导体材料制成的第二层内，以便与阵列和相关系统处理器通信。 由传感器单元组成的阵列可以使用柔性聚合物基底制造。 在有机半导体层上图案化触点之后，剥离基板并进行处置。 有机半导体层与反应性界面层一起使用，其被制成多余的以检测测试介质中的特定化学材料。 版权所有（C）2004，JPO
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Patent Agency Ranking
公开(公告)号：JP2004064093A
公开(公告)日：2004-02-26
申请号：JP2003280819
申请日：2003-07-28
Inventor： HARRY MICHAEL SIEGEL
CPC classification number: H01L23/36 , H01L23/3121 , H01L23/4006 , H01L23/4093 , H01L2023/4043 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/83191 , H01L2224/83192 , H01L2924/1815
Abstract: PROBLEM TO BE SOLVED: To provide an improved technology to remove heat from an active area of an integrated circuit device. SOLUTION: The method for removing heat from the active area 104 of the integrated circuit device is provided. A separating body 112 is imparted to the active area 104 of the integrated circuit device. A heat-conductive element 102 is joined to the active area 104 of the integrated circuit device on the outside of the separating body 112. COPYRIGHT: (C)2004,JPO
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17.发明专利
公开(公告)号：JP2007150367A
公开(公告)日：2007-06-14
申请号：JP2007061878
申请日：2007-03-12
Inventor： SMITH GREGORY C
IPC: C23F1/02 , H01L21/768 , C23F4/00 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L23/485 , H01L23/522
CPC classification number: H01L23/5226 , H01L21/76804 , H01L23/485 , H01L2924/0002 , Y10S438/97 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a technique for forming a contact opening which is hardly corroded when an interconnecting layer is formed.
SOLUTION: A contact opening is formed penetrating through an insulating layer 34 so that it has a straight sidewall part 42 and a bowl-shaped sidewall part 40. The bowl-shaped sidewall part 40 is located close to the top part of the insulating layer 34 to make the top part of the contact opening wider in diameter than its base. A conductive material 46 is formed inside the contact opening, electrically coming into contact with a lower conductive layer 32. The conductive material 46 forms a plug 47 having an enlarged head 52. The enlarged head 52 protects a barrier layer 45 located inside the contact opening against anisotropic etching which is carried out later. Therefore, when an electric interconnecting layer 48 of aluminum or the like is formed over the contact plug 47, the contact plug serves as an etching stopper to protect the barrier layer inside the contact opening against etching.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 要解决的问题：提供形成互连层时难以腐蚀的接触开口的技术。 解决方案：形成穿过绝缘层34的接触开口，使得其具有直的侧壁部分42和碗形的侧壁部分40.碗状的侧壁部分40位于接近开口部分的顶部 绝缘层34使接触开口的顶部比其底部的直径更宽。 导电材料46形成在接触开口内部，与下导电层32电接触。导电材料46形成具有扩大头52的插头47.扩大头52保护位于接触开口内的阻挡层45 抵抗随后进行的各向异性蚀刻。 因此，当在接触插塞47上形成铝等的电互连层48时，接触插塞用作蚀刻停止器，以保护接触开口内的阻挡层免受蚀刻。 版权所有（C）2007，JPO＆INPIT
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18.发明专利Burst error limiting feedback equalizer system and method of multidimensional modulation system 审中-公开爆发误差限制反馈均衡系统和多维度调制系统的方法
公开(公告)号：JP2006254460A
公开(公告)日：2006-09-21
申请号：JP2006064613
申请日：2006-03-09
Inventor： KORALEK RICHARD W
CPC classification number: H04L25/03267
Abstract: PROBLEM TO BE SOLVED: To provide technologies for reducing an error rate of data to be transferred or stored in a communication and a storage system. SOLUTION: A feedback equalizer circuit provides a feedback equalizer signal for canceling undesired distortion in an input signal. A summing circuit is responsive to the input signal and the feedback equalizer signal to provide a corrected sample signal to a symbol detector circuit. A feedback modification circuit is responsive to the corrected sample being within one of a plurality of valid symbol windows to feed back the detected symbol to the feedback equalizer and is responsive to the corrected sample being within one of a plurality of marginal threshold windows to feed back a corresponding intermediate value to the feedback equalizer. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供减少要传送或存储在通信和存储系统中的数据的错误率的技术。 解决方案：反馈均衡器电路提供反馈均衡器信号以消除输入信号中的不期望的失真。 求和电路响应于输入信号和反馈均衡器信号，以向符号检测器电路提供校正的采样信号。 反馈修改电路响应于在多个有效符号窗口之一内的校正样本，以将检测到的符号反馈到反馈均衡器，并且响应于在多个边缘阈值窗口之一内的校正样本反馈 与反馈均衡器相对应的中间值。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006108104A
公开(公告)日：2006-04-20
申请号：JP2005292453
申请日：2005-10-05
Inventor： ANTHONY M CHU
CPC classification number: H01M8/0612 , H01M8/04089 , H01M8/04201 , H01M8/04291 , H01M8/0656 , H01M8/186 , H01M2008/1095 , Y02E60/528
Abstract: PROBLEM TO BE SOLVED: To provide a fuel cell device capable of being structured as a cylindrical cell such as a conventional battery.
SOLUTION: The fuel cell device includes a housing including a fuel processor 40 generating fuel gas and a fuel cell 42 equipped with an electrode forming an anode 44 and a cathode 46, and an ion exchange electrolyte placed between the electrodes. The housing is formed as an exterior shell section with first and second cylindrical figures 32, 34 forming a battery cell structured same as a marketed cell. The electrode has a shape of forcing heat generated between the electrodes toward an end part of lower temperature of the electrode and putting back water for generation of hydrogen gas to the fuel processor by a pump action in a capillary action. The electrode is formed on a silicon substrate including a flow divider equipped with at least one fuel gas input channel capable of controlling with an MEMS valve.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供一种能够被构造为诸如常规电池的圆柱形电池的燃料电池装置。 解决方案：燃料电池装置包括壳体，其包括产生燃料气体的燃料处理器40和配备有形成阳极44和阴极46的电极的燃料电池42和置于电极之间的离子交换电解质。 壳体形成为具有第一和第二圆柱形图形32,32的外壳部分，形成与市售单元相同的电池单元。 电极具有在电极之间产生的热量朝向电极的较低温度的端部强迫的形状，并且通过毛细作用中的泵作用将用于产生氢气的氢回放到燃料处理器。 电极形成在硅衬底上，该衬底包括配备有能够利用MEMS阀控制的至少一个燃料气体输入通道的分流器。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006019009A
公开(公告)日：2006-01-19
申请号：JP2005191245
申请日：2005-06-30
Inventor： FREY CHRISTOPHE
IPC: G11C11/15
CPC classification number: G11C11/16
Abstract: PROBLEM TO BE SOLVED: To provide an improved magnetic random access memory array.
SOLUTION: The random access memory array includes random access memory elements arranged in a rows and columns. Each row is divided into a plurality of row groups of elements and each column is divided into a plurality of column groups of elements. The elements in each row group share a common local write digit line and the elements in each column group share a common local write bit line. The array further includes at least one global write digit line coupled to the common local write digit lines of a plurality of row groups, and at least one global write bit line coupled to the common local write bit lines of a plurality of column groups.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供一种改进的磁性随机存取存储器阵列。 解决方案：随机存取存储器阵列包括以行和列排列的随机存取存储器元件。 每行被分成多个行组元素，并且每列被分成多个列组元素。 每个行组中的元素共享一个公共的本地写入数字行，并且每个列组中的元素共享一个公共的本地写入位线。 阵列还包括耦合到多个行组的公共本地写入数字线的至少一个全局写入数字线以及耦合到多个列组的公共本地写入位线的至少一个全局写入位线。 版权所有（C）2006，JPO＆NCIPI
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