公开(公告)号：WO2005091545A1

公开(公告)日：2005-09-29

申请号：PCT/GB2005/001025

申请日：2005-03-18

Applicant: STMiCROELECTRONICS LIMITED ,  DELLOW, Andrew ,  BENNETT, Peter ,  CORDERO, Rodrigo

Inventor： DELLOW, Andrew ,  BENNETT, Peter ,  CORDERO, Rodrigo

IPC: H04L9/00

CPC classification number: H04N7/162 ,  G06F12/1408 ,  H04H60/23 ,  H04N7/1675

Abstract: In an embodiment of the invention, a memory is provided to store data in an encrypted form. A modifiab e register is arranged to store a memory address, a o , defining a boundary separating the memory into two regions. The tower region stores data encrypted using a key B, and the upper region stores data encrypted using a different key A. Data stored on the boundary address is encrypted using key A. Accordingly, when data is read from a memory address a, key A is used to decrypt the data if a≥a 0 , and key B is used if a 0 . However, when data is written to a memory address a, then key A is used to encrypt the data if a≥a 0 +1, key B is used if a 0 +1. The value of a 0 is .then incremented by one. When data is written to the boundary address, ao, the position of the boundary is thus caused to increase by one unit. Initially, the value of a 0 is set to zero so that all data within the memory is encrypted. using key A. As data is written to the memory, particularly on the boundary address, the value of ao gradually increases. Eventually the value of a 0 will exceed the highest address of the memory. At this point, all data within the memory is encrypted using key B, and a new key is generated. The new key becomes key B, and key A takes the value of the old key B. The value of a 0 is then set back to zero and the process is repeated. If a particular region of the memory is never written to, the value of a 0 will not increase beyond the lowest memory address of this region. To prevent this occurrence, if the value of a 0 does not change within a predetermined period of time then a `kicker' process is activated. During the kicker process, data is caused to be read from the memory address ao, and then to be written back to the same location, thereby artificially stimulating an increase of the value of a 0 .

Abstract translation: 在本发明的实施例中，提供存储器以以加密形式存储数据。 一个修改寄存器被设置为存储存储器地址，ao，定义将存储器分隔成两个区域的边界。 塔区存储使用密钥B加密的数据，上部区域存储使用不同密钥A加密的数据。使用密钥A对存储在边界地址上的数据进行加密。因此，当从存储器地址a读取数据时，密钥A 如果a = a0则用于解密数据，如果A = a0 + 1，则使用密钥A来加密数据，如果a <0 + 1则使用密钥B. a0的值再递增1。 当数据写入边界地址ao时，边界的位置因此增加一个单位。 最初，a0的值被设置为零，使得存储器内的所有数据被加密。 使用密钥A.由于数据被写入存储器，特别是在边界地址上，ao的值逐渐增加。 最终a0的值将超过内存的最高地址。 此时，使用密钥B对内存中的所有数据进行加密，并生成新的密钥。 新密钥成为密钥B，密钥A取旧密钥B的值。a0的值被设置为零，重复该过程。 如果存储器的特定区域从不被写入，则a0的值不会超出该区域的最低存储器地址。 为了防止发生这种情况，如果a0的值在预定的时间段内没有改变，则“踢球”进程被激活。 在踢球过程中，使数据从存储器地址ao读取，然后被写回相同位置，从而人为地刺激a0的值的增加。

公开(公告)号：WO2005059725A1

公开(公告)日：2005-06-30

申请号：PCT/GB2004/005327

申请日：2004-12-17

Applicant: STMICROELECTRONICS LIMITED ,  DELLOW, Andrew ,  GURNEY, Howard

Inventor： DELLOW, Andrew ,  GURNEY, Howard

IPC: G06F1/00

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F21/79 ,  G06F21/85

Abstract: A monolithic semiconductor integrated circuit is provided for selectively encrypting or decrypting data transmitted between one of a plurality of devices on the circuit and an external memory. Two series of data pathways connect the devices and the external memory. The first series of data pathways passes through a cryptographic circuit causing data to be encrypted or decrypted, and the other series of data pathways provides an unhindered route. When a data access request is made by a device, the data is selectively routed along one of the two series of data pathways according to the identification of the device making the data access request. In one example, if data is transmitted from a device to the external memory, the data is selectively encrypted before being stored in the external memory if the device transmitting the data is identified as secure. Then, when that data is retrieved from the external memory by a second device, the data is selectively decrypted only if the second device is identified as secure.

Abstract translation: 提供单片半导体集成电路，用于选择性地加密或解密在电路上的多个设备之一和外部存储器之间传输的数据。 两组数据通路连接设备和外部存储器。 数据路径的第一系列通过加密电路，导致数据被加密或解密，另一系列的数据路径提供了一个不受阻碍的路由。 当设备进行数据访问请求时，根据进行数据访问请求的设备的标识，数据沿着两个数据路径中的一个选择性地路由选择。 在一个示例中，如果数据从设备发送到外部存储器，则如果发送数据的设备被识别为安全的，则在被存储在外部存储器中之前，数据被选择性地加密。 然后，当通过第二设备从外部存储器检索数据时，只有当第二设备被识别为安全时才选择性地解密该数据。

公开(公告)号：WO2005055611A1

公开(公告)日：2005-06-16

申请号：PCT/GB2004/004924

申请日：2004-11-23

Applicant: STMICROELECTRONICS LIMITED ,  STMICROELECTRONICS Srl ,  BOLTON, Martin ,  CARRANO, Michele

Inventor： BOLTON, Martin ,  CARRANO, Michele

IPC: H04N7/26

CPC classification number: H04N7/24 ,  H04N19/42

Abstract: A video decoding circuit comprising: a first video data processor; a second video data processor; and a connection connecting the first video data processor and the second data processor; wherein the first video data processor is arranged to receive a first signal comprising encoded video data, process the first signal to provide a second signal and output said second signal. The first video data processor being arranged to process the first signal dependent on at least part of the received first signal. The second video data processor is arranged to receive at least a part of the second signal, process the at least a part of the second signal to provide a third signal, and output the third signal, the second and third signals comprising a decoded video image stream. The second video data processor is arranged to process the at least part of the second signal dependent on at least part of the at least part of second signal.

Abstract translation: 一种视频解码电路，包括：第一视频数据处理器; 第二视频数据处理器; 以及连接第一视频数据处理器和第二数据处理器的连接; 其中所述第一视频数据处理器被布置为接收包括编码视频数据的第一信号，处理所述第一信号以提供第二信号并输出​​所述第二信号。 第一视频数据处理器被配置为根据接收的第一信号的至少一部分来处理第一信号。 第二视频数据处理器被布置成接收第二信号的至少一部分，处理第二信号的至少一部分以提供第三信号，并输出第三信号，第二和第三信号包括解码视频图像 流。 第二视频数据处理器被配置为根据第二信号的至少部分的至少一部分来处理第二信号的至少一部分。

公开(公告)号：WO2005046233A1

公开(公告)日：2005-05-19

申请号：PCT/GB2003/004480

申请日：2003-10-16

Applicant: STMICROELECTRONICS LIMITED ,  BENNETT, Peter ,  ELLIOTT, Paul ,  DELLOW, Andrew

Inventor： BENNETT, Peter ,  ELLIOTT, Paul ,  DELLOW, Andrew

IPC: H04N7/16

CPC classification number: H04N21/44 ,  H04N7/165 ,  H04N21/26606 ,  H04N21/42623 ,  H04N21/6334

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals comprises an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. The semiconductor integrated circuit is provided with some functionality restricted in some way by preventing one or more hardware circuit elements from operating, such as an MPEG decoder, display engine, IO ports or main CPU. To enable the functionality, a subscriber must pay for a service and then receives an encrypted message broadcast to the semiconductor integrated circuit which is decrypted and instructs functionality to be turned on or off.

Abstract translation: 用于处理条件接收电视信号的半导体集成电路包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 半导体集成电路具有通过防止一个或多个硬件电路元件操作（例如MPEG解码器，显示引擎，IO端口或主CPU）以某种方式受到限制的某些功能。 为了实现该功能，用户必须支付服务费用，然后接收加密消息广播到半导体集成电路，该半导体集成电路被解密并指示功能被打开或关闭。

公开(公告)号：US20040263217A1

公开(公告)日：2004-12-30

申请号：US10827675

申请日：2004-04-19

Applicant: STMicroelectronics Limited

Inventor： Matt Hutson ,  Andrew Dellow ,  Tom Ryan ,  Paul Elliott

IPC: H03K003/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

公开(公告)号：US20040257365A1

公开(公告)日：2004-12-23

申请号：US10811481

申请日：2004-03-26

Applicant: STMicroelectronics Limited

Inventor： Mathieu Robart

IPC: G06T015/60

CPC classification number: G06T15/60

Abstract: An image is rendered which includes at least one light source, a first, shadow-casting object with a second, shadow-receiving object located on the side of the first shadow-casting object remote from said at least one light source. A shadow mask is generated which identifies for each of a plurality of pixels on the shadow receiving surface a grey level representing the intensity of shadow in each pixel. The intensity is determined utilizing the distance between the shadow-casting object and the shadow-receiving object.

Abstract translation: 渲染图像，其包括至少一个光源，第一阴影投射对象，其具有位于远离所述至少一个光源的第一阴影投射对象的一侧上的第二影子接收对象。 产生阴影掩模，其对阴影接收表面上的多个像素中的每一个识别代表每个像素中的阴影强度的灰度级。 使用阴影投射对象和阴影接收对象之间的距离来确定强度。

公开(公告)号：US20040223618A1

公开(公告)日：2004-11-11

申请号：US10773089

申请日：2004-02-03

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H04L009/00

CPC classification number: H04L9/0631 ,  H04L9/0827 ,  H04L2209/601

Abstract: A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and to selectively provide the encrypted or decrypted data to at least one of the data destinations; an instruction interpreter arranged to receive an instruction signal and to generate an output to control the plurality of selectable pathways to select from which of the data sources the cryptographic circuit receives data and to which destination the cryptographic circuit provides data. The instruction interpreter configured such that the instruction signal defines a data pathway that operates in accordance with a rule that limits the data pathway configurations which are selectable.

Abstract translation: 一种具有与数据源和数据目的地相互连接的多个可选路径的半导体集成电路; 连接到所述可选择路径以选择性地从所述数据源中的至少一个数据源接收数据的密码电路，根据密钥对所述数据进行解密或加密，并且选择性地将加密或解密的数据提供给所述数据目的地中的至少一个 ; 指令解释器，被布置为接收指令信号并产生输出以控制多个可选路径，以从密码电路中的哪一个数据源接收数据以及加密电路提供数据的哪个目的地。 指令解释器被配置为使得指令信号定义根据限制可选择的数据路径配置的规则操作的数据通路。

公开(公告)号：US20040160349A1

公开(公告)日：2004-08-19

申请号：US10385202

申请日：2003-03-10

Applicant: STMicroelectronics Limited

Inventor： Arnaud Laflaquiere

IPC: H03M001/66 ,  H03M001/78

CPC classification number: G06J1/00 ,  H03K4/026

Abstract: A ramp generator includes a resistance ladder supplied with a constant current. Switches are closed in sequence on the resistance ladder to generate the ramp voltage. By using control logic to decode the sequence, a looped shift register is used to close the switches.

Abstract translation: 斜坡发生器包括提供恒定电流的电阻梯。 开关按顺序关闭在电阻梯以产生斜坡电压。 通过使用控制逻辑来解码序列，使用循环移位寄存器来关闭开关。

公开(公告)号：US20040030839A1

公开(公告)日：2004-02-12

申请号：US10278772

申请日：2002-10-22

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Peter Hedinger

IPC: G06F012/08

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/502 ,  G06F2212/6026

Abstract: A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.

Abstract translation: 高速缓存存储器包括：提取引擎，被配置为发出用于从正在执行的程序中的访问地址识别的主存储器中的位置访问数据项的提取请求，控制的预取引擎发布用于推测访问预取的预取请求 来自所述主存储器中的位置的数据项，其由被确定为来自所述访问地址的相应位置的位置的数量确定;以及校准器，被配置为选择性地改变所述位置数。

公开(公告)号：US20030161397A1

公开(公告)日：2003-08-28

申请号：US10159954

申请日：2002-05-31

Applicant: STMicroelectronics Limited

Inventor： Victor Watson ,  Jean-Jacques de Jong

IPC: H04N007/12

CPC classification number: H04N19/86 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61

Abstract: A method for performing a reordering operation on a matrix of input data values, the method comprising: loading the data values into a computer store by forming a plurality of data strings, each data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values, and storing each data string in a register of the computer store in which its sub-strings are not individually addressable; and performing a series of data reordering steps operating on one or more of said data strings to reorder said data values; the reordering operation being a scan-wise reordering operation.

Abstract translation: 一种用于对输入数据值的矩阵执行重排序操作的方法，所述方法包括：通过形成多个数据串将数据值加载到计算机存储器中，每个数据串包括多个数据子串和每个数据子 - 字符串表示数据值中的至少一个，并将每个数据串存储在其子串不能单独寻址的计算机存储的寄存器中; 以及执行对一个或多个所述数据串进行操作的一系列数据重排序步骤，以重新排列所述数据值; 重排序操作是扫描式重排序操作。