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公开(公告)号：US20130222053A1
公开(公告)日：2013-08-29
申请号：US13854395
申请日：2013-04-01
Applicant: STMicroelectronics R&D (Shanghai) Co., Ltd.
Inventor： Jian Hua ZHAO , Wadeo Ou
IPC: H03G3/00
CPC classification number: H03G3/004 , H03G3/002 , H03G3/3089
Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.
Abstract translation: 实现功率高效的高频缓冲器的电路和方法。 检测缓冲信号的幅度并与输入信号的幅度进行比较。 比较结果可以反馈到数字控制缓冲器，以保持输出增益不变。 通过使用反馈控制，即使负载条件或信号频率变化，也可以将缓冲器保持在最合适的偏置状态。
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公开(公告)号：US09000811B2
公开(公告)日：2015-04-07
申请号：US14199313
申请日：2014-03-06
Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.
Inventor： Fei Wang , Wen Li Bai
CPC classification number: H03K17/00 , H03K17/163
Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.
Abstract translation: 具有漏极和源极的驱动晶体管的栅极由包括感测电路的电路放电，该感测电路被配置为感测驱动晶体管的漏极 - 源极电压。 第一电流吸收通路耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较低的漏极 - 源极电压时，第一电流阱路径向驱动晶体管的栅极施加高放电电流。 第二电流吸收通路也耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较高的漏极 - 源极电压时，第二电流吸收通道被配置为向驱动晶体管的栅极施加低放电电流。
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公开(公告)号：US20140266322A1
公开(公告)日：2014-09-18
申请号：US14199313
申请日：2014-03-06
Applicant: STMICROELECTRONICS R&D (SHANGHAI) CO. LTD.
Inventor： Fei Wang , Wen Li Bai
IPC: H03K3/012
CPC classification number: H03K17/00 , H03K17/163
Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.
Abstract translation: 具有漏极和源极的驱动晶体管的栅极由包括感测电路的电路放电，该感测电路被配置为感测驱动晶体管的漏极 - 源极电压。 第一电流吸收通路耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较低的漏极 - 源极电压时，第一电流阱路径向驱动晶体管的栅极施加高放电电流。 第二电流吸收通路也耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较高的漏极 - 源极电压时，第二电流吸收通道被配置为向驱动晶体管的栅极施加低放电电流。
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公开(公告)号：US20140165079A1
公开(公告)日：2014-06-12
申请号：US14180894
申请日：2014-02-14
Applicant: STMicroelectronics R&D (Shanghai) Co., Ltd.
Inventor： Christophe Quarre , Maoping Weng , Zhe Wu
IPC: G06F9/54
CPC classification number: G06F9/54 , G06F9/44521
Abstract: The present invention provides a technical solution for a unified driver used in a handheld device. An embodiment of the technical solution may comprise a unified driving method used in a handheld device, which method may comprise: determining driver types of currently installed hardware; setting a current dispatch table on the basis of the driver type and a unified dispatch table suitable for multiple hardware and driving corresponding hardware or software by calling the current dispatch table.
Abstract translation: 本发明提供了用于手持设备中的统一驱动程序的技术方案。 技术方案的实施例可以包括在手持设备中使用的统一驱动方法，该方法可以包括：确定当前安装的硬件的驱动器类型; 基于驱动程序类型设置当前调度表，并通过调用当前调度表来适用于多个硬件并驱动相应的硬件或软件的统一调度表。
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公开(公告)号：US20140070788A1
公开(公告)日：2014-03-13
申请号：US14020949
申请日：2013-09-09
Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.
Inventor： Ansgar Pottbaecker , Panny Cai
IPC: G05F3/08
Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.
Abstract translation: 带隙参考电压发生器包括具有第一电阻器，第一分支和与第一分支平行的第二分支的双极组件。 第一分支包括具有耦合到固定电压的基极的第一双极晶体管。 第二分支包括具有耦合到固定电压的基极的第二双极晶体管和与第二双极晶体管串联耦合的第二电阻器。 差分模块耦合到第一和第二双极晶体管并且被配置为平衡第一和第二分支中的电流。 带隙参考电压在与第一电阻器连接的节点处输出。
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Patent Agency Ranking
公开(公告)号：US09568933B2
公开(公告)日：2017-02-14
申请号：US14020949
申请日：2013-09-09
Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.
Inventor： Ansgar Pottbaecker , Panny Cai
Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.
Abstract translation: 带隙参考电压发生器包括具有第一电阻器，第一分支和与第一分支平行的第二分支的双极组件。 第一分支包括具有耦合到固定电压的基极的第一双极晶体管。 第二分支包括具有耦合到固定电压的基极的第二双极晶体管和与第二双极晶体管串联耦合的第二电阻器。 差分模块耦合到第一和第二双极晶体管并且被配置为平衡第一和第二分支中的电流。 带隙参考电压在与第一电阻器连接的节点处输出。
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公开(公告)号：US08813099B2
公开(公告)日：2014-08-19
申请号：US14180894
申请日：2014-02-14
Applicant: STMicroelectronics R&D (Shanghai) Co., Ltd.
Inventor： Christophe Quarre , Maoping Weng , Zhe Wu
CPC classification number: G06F9/54 , G06F9/44521
Abstract: The present invention provides a technical solution for a unified driver used in a handheld device. An embodiment of the technical solution may comprise a unified driving method used in a handheld device, which method may comprise: determining driver types of currently installed hardware; setting a current dispatch table on the basis of the driver type and a unified dispatch table suitable for multiple hardware and driving corresponding hardware or software by calling the current dispatch table.
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公开(公告)号：US20130173949A1
公开(公告)日：2013-07-04
申请号：US13716029
申请日：2012-12-14
Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.
Inventor： Panny Cai , Martin Huag
IPC: G06F1/04
CPC classification number: G06F1/04 , G06F3/044 , G06F11/3051
Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.
Abstract translation: 一种用于恢复CAN总线的时钟频率的方法，所述方法包括：接收数据信号，其中所述数据信号包括至少一个状态转换; 检测状态转换; 以及调整由振荡器电路产生的时钟信号的频率，其中当检测到状态转换时调整频率，并且调整频率用于恢复CAN总线的时钟频率。
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公开(公告)号：US20130169344A1
公开(公告)日：2013-07-04
申请号：US13657930
申请日：2012-10-23
Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.
Inventor： Ming Jiang , Jerry Cui
IPC: H03K17/693
CPC classification number: H03K17/102
Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed
Abstract translation: 驱动电路包括具有设计最大电压V2的开关晶体管和具有设计最大电压V1的共源共栅晶体管，其中共源共栅晶体管是与开关晶体管串联耦合的源极 - 漏极。 电路还包括耦合在中间电压节点和共源共栅晶体管的栅极之间的电流源。 如果驱动电路是低端驱动器，则中间电压节点接收设置在高电源电压Vhigh以下的中间电压Vmed，并满足以下条件：a）Vmed <= V2和b）Vhigh-Vmed <= V1。 如果驱动电路是高侧驱动器，则中间电压节点接收低于高电源电压的中间电压Vmed，并且符合以下条件：a）Vmed <= V1和b）Vhigh-Vmed <= V2。 该电路可以通过将高侧驱动器和低侧驱动器串联耦合而构造为推挽驱动器。
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公开(公告)号：US09032239B2
公开(公告)日：2015-05-12
申请号：US13716029
申请日：2012-12-14
Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.
Inventor： Panny Cai , Martin Haug
CPC classification number: G06F1/04 , G06F3/044 , G06F11/3051
Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.
Abstract translation: 一种用于恢复CAN总线的时钟频率的方法，所述方法包括：接收数据信号，其中所述数据信号包括至少一个状态转换; 检测状态转换; 以及调整由振荡器电路产生的时钟信号的频率，其中当检测到状态转换时调整频率，并且调整频率用于恢复CAN总线的时钟频率。
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