公开(公告)号：US07292486B2

公开(公告)日：2007-11-06

申请号：US11008462

申请日：2004-12-09

Applicant: Sang-bo Lee

Inventor： Sang-bo Lee

IPC: G11C7/00

CPC classification number: G11C7/1066 ,  G11C7/1039 ,  G11C7/1072

Abstract: Methods of providing a delay for access to a memory device can include adjusting a delay for access to data during memory operations based on at least one parameter associated with a reduction in voltage levels provided to the memory. Related circuits are also disclosed.

Abstract translation: 提供对存储设备的访问的延迟的方法可以包括基于与提供给存储器的电压电平的降低相关联的至少一个参数来调整在存储器操作期间对数据的访问的延迟。 还公开了相关电路。

公开(公告)号：US07219026B2

公开(公告)日：2007-05-15

申请号：US11031104

申请日：2005-01-07

Applicant: Hyun-Jin Kim ,  Sang-Bo Lee

Inventor： Hyun-Jin Kim ,  Sang-Bo Lee

IPC: G06F19/00

CPC classification number: G11C7/22 ,  G11C7/16 ,  G11C7/222

Abstract: A frequency measuring circuit may include an edge detector, a charge pump, and an analog-to-digital (A/D) converter. The edge detector may be configured to generate an output pulse responsive to an edge of an input clock signal. The charge pump may be configured to generate an output signal responsive to the output pulse from the edge detector. The analog-to-digital (A/D) converter may be configured to convert the output signal into a digital value representing a frequency of the input clock signal. Related methods and integrated circuit memory devices are also discussed.

Abstract translation: 频率测量电路可以包括边缘检测器，电荷泵和模数（A / D）转换器。 边缘检测器可以被配置为响应于输入时钟信号的边缘产生输出脉冲。 电荷泵可以被配置为响应于来自边缘检测器的输出脉冲而产生输出信号。 模拟数字（A / D）转换器可以被配置为将输出信号转换成表示输入时钟信号的频率的数字值。 还讨论了相关方法和集成电路存储器件。

公开(公告)号：US20050254337A1

公开(公告)日：2005-11-17

申请号：US11188708

申请日：2005-07-26

Applicant: Sang-bo Lee ,  Ho-young Song

Inventor： Sang-bo Lee ,  Ho-young Song

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00

CPC classification number: G11C7/1066 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2281

Abstract: The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

Abstract translation: 存储器件包括存储器单元阵列和从存储单元阵列寻址的数据的输出缓冲器，并且基于等待时间信号输出数据。 延迟电路基于CAS等待时间信息选择性地将至少一个传送信号与至少一个采样信号相关联，以在相关联的采样和传送信号之间产生期望的时序关系。 延迟电路根据至少一个采样信号存储读取信息，并且基于与用于存储读取的信息的采样信号相关联的传送信号产生等待时间信号。

公开(公告)号：US20050195672A1

公开(公告)日：2005-09-08

申请号：US11068353

申请日：2005-02-28

Applicant: Sang-Bo Lee

Inventor： Sang-Bo Lee

IPC: G11C7/06 ,  G11C7/02 ,  G11C11/4091 ,  G11C11/419

CPC classification number: G11C11/4091 ,  G11C7/04

Abstract: A current sense amplifier includes first and second P type MOS transistors having source nodes connected to first and second sensing inputs, respectively, and gate and drain nodes being cross-coupled to each other. First and second N type MOS transistors have drain nodes connected to first and second sensing outputs, respectively, the first and second sensing outputs corresponding to the drain nodes of the first and second P type MOS transistors, respectively, the first and second N type MOS transistors having respective gate nodes connected to a power supply voltage. Third and fourth N type MOS transistors have drain nodes connected to the first and second sensing outputs, respectively, and gate nodes connected to a bias voltage node so that respective current paths are established from the first and second sensing outputs to a common reference node.

Abstract translation: 电流检测放大器包括分别连接到第一和第二感测输入的源节点的第一和第二P型MOS晶体管，并且栅极和漏极节点彼此交叉耦合。 第一和第二N型MOS晶体管具有分别连接到第一和第二感测输出的漏极节点，分别对应于第一和第二P型MOS晶体管的漏极节点的第一和第二感测输出，第一和第二N型MOS 具有连接到电源电压的各个栅极节点的晶体管。 第三和第四N型MOS晶体管分别具有连接到第一和第二感测输出的漏极节点，以及连接到偏置电压节点的栅极节点，使得各自的电流路径从第一和第二感测输出建立到公共参考节点。

公开(公告)号：US06356489B2

公开(公告)日：2002-03-12

申请号：US09766358

申请日：2001-01-19

Applicant: Sang-bo Lee

Inventor： Sang-bo Lee

IPC: G11C700

CPC classification number: G11C7/109 ,  G11C7/1078 ,  G11C7/22

Abstract: A semiconductor memory device having an operation delay function of a CAS command, and a buffer and a signal transmission circuit which are applied to the semiconductor memory device, are provided. The signal transmission circuit includes a plurality of transmission units each for delaying an input signal by a different number of delay clock cycles. The transmission unit includes a transmission switch and a clock delay unit. The semiconductor memory device can delay a received signal for different numbers of delay clocks in response to first through third control signals. Therefore, a predetermined delay time between when a row-type command is received and when a column-type command is received can be shortened.

Abstract translation: 提供具有CAS命令的操作延迟功能的半导体存储器件，以及应用于半导体存储器件的缓冲器和信号传输电路。 信号传输电路包括多个传输单元，每个传输单元用于将输入信号延迟不同数量的延迟时钟周期。 传输单元包括传输开关和时钟延迟单元。 半导体存储器件可以响应于第一至第三控制信号而延迟不同数量的延迟时钟的接收信号。 因此，可以缩短接收行类型命令与列类型命令之间的预定延迟时间。

公开(公告)号：US09000572B2

公开(公告)日：2015-04-07

申请号：US13567394

申请日：2012-08-06

Applicant: Hoon Lee ,  Sang-Bo Lee

Inventor： Hoon Lee ,  Sang-Bo Lee

IPC: H01L23/02 ,  H01L21/00 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17135 ,  H01L2224/17136 ,  H01L2224/17517 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate may include a first semiconductor chip, a second semiconductor chip, plugs and interconnection terminals. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The first and second semiconductor chips may have corresponding first regions and corresponding second regions. Conductive plugs may be built only in a first region of the first semiconductor chip. Circuitry of the second semiconductor chip may only be electrically connected to the first semiconductor chip through the conductive connectors corresponding to the first regions of the first and second semiconductor chips.

Abstract translation: 半导体封装基板可以包括第一半导体芯片，第二半导体芯片，插头和互连端子。 第二半导体芯片可以布置在第一半导体芯片的上表面上。 第一和第二半导体芯片可以具有对应的第一区域和对应的第二区域。 导电插头可以仅构建在第一半导体芯片的第一区域中。 第二半导体芯片的电路只能通过对应于第一和第二半导体芯片的第一区域的导电连接器与第一半导体芯片电连接。

公开(公告)号：US20140223257A1

公开(公告)日：2014-08-07

申请号：US14165820

申请日：2014-01-28

Applicant: Chi-Sung OH ,  Chul-Sung PARK ,  Sang-Bo LEE ,  Dong-Hyun SOHN

Inventor： Chi-Sung OH ,  Chul-Sung PARK ,  Sang-Bo LEE ,  Dong-Hyun SOHN

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/16 ,  G11C11/005 ,  G11C11/40 ,  G11C11/4076 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Abstract translation: 公开了可以使用纠错电路校正错误数据的半导体存储器件。 半导体存储器件可以包括DRAM单元阵列，奇偶校验发生器，非易失性存储单元阵列和纠错电路。 奇偶校验发生器被配置为基于输入数据生成具有至少一个位的第一组奇偶校验位。 非易失性存储单元阵列可以存储对应于输入数据的输入数据和第一组奇偶校验位，并且输出与输入数据相对应的第一数据，以及对应于第一组奇偶校验位的第二组奇偶校验位。 误差校正电路被配置为基于第一数据生成作为校正数据的第二数据。

公开(公告)号：US20070195625A1

公开(公告)日：2007-08-23

申请号：US11789395

申请日：2007-04-24

Applicant: Sang-Bo Lee

Inventor： Sang-Bo Lee

IPC: G11C7/00 ,  G11C5/06

CPC classification number: G11C7/18 ,  G11C7/062

Abstract: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

Abstract translation: 存储器件包括一个解码器，它同时设置第一逻辑电平的操作控制信号和列选择线信号。 另外，本地读出放大器具有至少一个开关装置，该开关装置由处于第一逻辑电平的操作控制信号导通，以将至少一个本地I / O线耦合到至少一个全局I / O线。 此外，被设置为并联的信号线从解码器发送操作控制信号和列选择线信号。

公开(公告)号：US20060250162A1

公开(公告)日：2006-11-09

申请号：US11379200

申请日：2006-04-18

Applicant: Du-Yeul Kim ,  Jun-Hyung Kim ,  Tai-Young Ko ,  Sang-Bo Lee

Inventor： Du-Yeul Kim ,  Jun-Hyung Kim ,  Tai-Young Ko ,  Sang-Bo Lee

IPC: H03F3/45

CPC classification number: G11C7/1072 ,  G11C7/1051 ,  G11C7/1069

Abstract: A signal amplification circuit for a semiconductor memory device includes a current sense amplifier configured to receive a first signal pair and generate a second signal pair on a first pair of lines, an equalizer configured to equalize the first pair of lines, and a latch amplifier configured to generate a latch data output on a second pair of lines in response to the second signal pair.

Abstract translation: 一种用于半导体存储器件的信号放大电路包括：电流检测放大器，被配置为接收第一信号对并在第一对线路上产生第二信号对，配置成对第一对线路进行均衡的均衡器和配置成 以响应于第二信号对在第二对线路上产生锁存数据输出。

公开(公告)号：US07038963B2

公开(公告)日：2006-05-02

申请号：US11068353

申请日：2005-02-28

Applicant: Sang-Bo Lee

Inventor： Sang-Bo Lee

IPC: G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/04

Abstract: A current sense amplifier includes first and second P type MOS transistors having source nodes connected to first and second sensing inputs, respectively, and gate and drain nodes being cross-coupled to each other. First and second N type MOS transistors have drain nodes connected to first and second sensing outputs, respectively, the first and second sensing outputs corresponding to the drain nodes of the first and second P type MOS transistors, respectively, the first and second N type MOS transistors having respective gate nodes connected to a power supply voltage. Third and fourth N type MOS transistors have drain nodes connected to the first and second sensing outputs, respectively, and gate nodes connected to a bias voltage node so that respective current paths are established from the first and second sensing outputs to a common reference node.

Abstract translation: 电流检测放大器包括分别连接到第一和第二感测输入的源节点的第一和第二P型MOS晶体管，并且栅极和漏极节点彼此交叉耦合。 第一和第二N型MOS晶体管具有分别连接到第一和第二感测输出的漏极节点，分别对应于第一和第二P型MOS晶体管的漏极节点的第一和第二感测输出，第一和第二N型MOS 具有连接到电源电压的各个栅极节点的晶体管。 第三和第四N型MOS晶体管分别具有连接到第一和第二感测输出的漏极节点，以及连接到偏置电压节点的栅极节点，使得各自的电流路径从第一和第二感测输出建立到公共参考节点。