公开(公告)号：WO2013036395A1

公开(公告)日：2013-03-14

申请号：PCT/US2012/052525

申请日：2012-08-27

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC. ,  KW LEUNG, Andrew ,  TOPACIO, Roden, R. ,  HSIEH, Yu-Ling ,  LOW, Yip, Seng

Inventor： KW LEUNG, Andrew ,  TOPACIO, Roden, R. ,  HSIEH, Yu-Ling ,  LOW, Yip, Seng

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81401 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83385 ,  H01L2224/83862 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/05552

Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening (125) in a solder mask (115) positioned on a side (117) of a substrate (20). The first opening (125) does not extend to the side (117). A second opening (119) is formed in the solder mask that extends to the side. The first opening (125) may serve as an underfill anchor site.

Abstract translation: 公开了用于接收半导体芯片的各种基板或电路板及其处理方法。 一方面，提供了一种制造方法，其包括在位于基板（20）的侧面（117）上的焊料掩模（115）中形成第一开口（125）。 第一开口（125）不延伸到侧面（117）。 在向侧面延伸的焊料掩模中形成第二开口（119）。 第一开口（125）可以用作底部填充锚点。

公开(公告)号：WO2013032956A2

公开(公告)日：2013-03-07

申请号：PCT/US2012/052408

申请日：2012-08-25

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC. ,  TOPACIO, Roden, R. ,  MCLELLAN, Neil

Inventor： TOPACIO, Roden, R. ,  MCLELLAN, Neil

IPC: H01L21/60

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/115 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/06 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures (60, 60') and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a first layer (85) of a first metallic material on a semiconductor chip (15). The first layer (85) has a first physical quantity. A second layer (190) of a second metallic material is deposited on the first layer (85) of the first metallic material. The second layer (190) has a second physical quantity. The first and second layers (85), (190) are reflowed to form a solder structure (35) with a desired ratio of the first metallic material to the second metallic material.

Abstract translation: 公开了各种半导体芯片焊料凸块和底部金属化（UBM）结构（60,60'）及其制造方法。 一方面，提供一种方法，其包括在半导体芯片（15）上沉积第一金属材料的第一层（85）。 第一层（85）具有第一物理量。 第二金属材料的第二层（190）沉积在第一金属材料的第一层（85）上。 第二层（190）具有第二物理量。 第一和第二层（85），（190）被回流以形成具有所需比率的第一金属材料与第二金属材料的焊料结构（35）。

公开(公告)号：WO2010069077A1

公开(公告)日：2010-06-24

申请号：PCT/CA2009/001861

申请日：2009-12-18

Applicant: ATI TECHNOLOGIES ULC ,  MARTINEZ, Liane ,  TOPACIO, Roden, R. ,  LOW, Yip, Seng

Inventor： MARTINEZ, Liane ,  TOPACIO, Roden, R. ,  LOW, Yip, Seng

IPC: H01L21/77 ,  H01L21/60 ,  H01L21/98 ,  H01L23/485 ,  H01L23/488 ,  H01L23/50

CPC classification number: G06F17/5068 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/85181 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/92127 ,  H01L2224/92163 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2224/11 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

Abstract translation: 集成电路（IC）产品包括具有至少一个导电层的再分配层（RDL），该导电层被配置为将电信息从一个位置分配到IC中的另一个位置。 RDL还包括多个引线接合焊盘和多个焊盘。 多个焊盘各自包括与RDL直接电连通的焊料可润湿材料。

公开(公告)号：WO2008026077A2

公开(公告)日：2008-03-06

申请号：PCT/IB2007/003615

申请日：2007-08-31

Applicant: ATI TECHNOLOGIES, ULC ,  MCLELLAN, Neil, R. ,  CHAN, Vincent, K. ,  TOPACIO, Roden, R.

Inventor： MCLELLAN, Neil, R. ,  CHAN, Vincent, K. ,  TOPACIO, Roden, R.

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An integrated circuit package includes an encapsulant retention structure located adjacent to a die on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the die. The retention structure placed on the substrate may also serve as a substrate stiffener to maintain mechanical properties of the substrate, allowing use of a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener allows passive electronic components to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, where a larger strip with a plurality of integrated circuit packages is produced industrially and then singulated.

Abstract translation: 集成电路封装包括邻近衬底上的管芯的密封剂保留结构。 该结构允许更大量的密封剂的放置和保持在模具下渗出。 放置在基板上的保持结构也可以用作基板加强件，以保持基板的机械性能，允许使用更理想的更薄的基板。 在一个实施例中，在加强件中使用开口和凹槽允许无源电子部件在使用更薄的衬底时保持机械性能。 使用保留壁或加强件允许使用条带，矩阵来制造这些集成电路封装，其中具有多个集成电路封装的较大条带在工业上制造然后被分割。