公开(公告)号：US20110141318A1

公开(公告)日：2011-06-16

申请号：US12955287

申请日：2010-11-29

Applicant: Yun Tae Lee ,  Joon Seo Yim ,  Je Suk Lee ,  Jae Yong Park ,  Jun-Woo Park ,  Su-Young Lee

Inventor： Yun Tae Lee ,  Joon Seo Yim ,  Je Suk Lee ,  Jae Yong Park ,  Jun-Woo Park ,  Su-Young Lee

IPC: H04N5/262 ,  H04N5/228

CPC classification number: H04N5/23296 ,  H01L27/14618 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/12044 ,  H04N5/2257 ,  H04N5/3454 ,  H04N5/374 ,  H04N5/378 ,  H04N9/045 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An image sensor module is provided. The image sensor module includes a printed circuit board (PCB), an image sensor chip disposed on a first plane of the PCB and electrically connected to the PCB, and an image signal processing chip disposed on the first plane of the PCB and electrically connected to the PCB. An aspect ratio of the image signal processing chip is at least two times greater than an aspect ratio of the image sensor chip. A minimum feature size of a metal line implemented in the image sensor chip is at least 1.5 times greater than a minimum feature size of a metal line implemented in the image signal processing chip.

Abstract translation: 提供图像传感器模块。 图像传感器模块包括印刷电路板（PCB），设置在PCB的第一平面上并电连接到PCB的图像传感器芯片，以及设置在PCB的第一平面上并且电连接到 PCB。 图像信号处理芯片的纵横比比图像传感器芯片的纵横比至少大两倍。 在图像传感器芯片中实现的金属线的最小特征尺寸比图像信号处理芯片中实施的金属线的最小特征尺寸至少大1.5倍。

公开(公告)号：US07873822B2

公开(公告)日：2011-01-18

申请号：US11797985

申请日：2007-05-09

Applicant: Yong-Hoon Kim ,  Yun-Tae Lee ,  Sung-Up Choi

Inventor： Yong-Hoon Kim ,  Yun-Tae Lee ,  Sung-Up Choi

IPC: G06F15/177

CPC classification number: G06F9/4401

Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

Abstract translation: 电子信息系统包括外部存储装置和应用处理器。 外部存储装置存储引导代码，并且应用处理器适于从外部存储设备接收引导代码，并且在上电操作期间通过执行引导代码执行系统引导操作。

公开(公告)号：US07539825B2

公开(公告)日：2009-05-26

申请号：US11345054

申请日：2006-02-01

Applicant: Han-Gu Sohn ,  Woon-Sik Suh ,  Yun-Tae Lee ,  Sei-Jin Kim

Inventor： Han-Gu Sohn ,  Woon-Sik Suh ,  Yun-Tae Lee ,  Sei-Jin Kim

IPC: G06F12/00 ,  G06F13/18

CPC classification number: G11C7/1075 ,  G06F13/1647 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1063 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4096

Abstract: A memory system includes a first external device, a second external device, and a multi-port memory device connected to the first and second external devices. The multi-port memory system includes: a first port and a second port connected to the first and second external devices, respectively, a first bank group having at least one memory bank, the first bank group configured to be accessed by the first external device through the first data port; a second bank group having at least one memory bank, the second bank group configured to be accessed by the second external device through the second data port; a third bank group having at least one memory bank, wherein the third bank group is configured to be selectively accessed by the first external device through the first data port or the second external device through the second data port. The multi-port memory system may prevent data collisions which occur when two ports simultaneously attempt to access the same memory bank.

Abstract translation: 存储器系统包括连接到第一和第二外部设备的第一外部设备，第二外部设备和多端口存储设备。 多端口存储器系统包括：分别连接到第一和第二外部设备的第一端口和第二端口，具有至少一个存储体的第一组组，第一组组被配置为由第一外部设备 通过第一个数据端口; 具有至少一个存储体的第二组组，所述第二组组被配置为通过所述第二数据端口被所述第二外部设备访问; 具有至少一个存储体的第三组组，其中所述第三组组被配置为通过所述第一数据端口或所述第二外部设备通过所述第二数据端口被所述第一外部设备选择性地访问。 多端口存储器系统可以防止当两个端口同时尝试访问同一存储体时发生的数据冲突。

公开(公告)号：US20090044077A1

公开(公告)日：2009-02-12

申请号：US12187427

申请日：2008-08-07

Applicant: SUNG UP CHOI ,  Yun-Tae Lee ,  Sung-Man Hwang

Inventor： SUNG UP CHOI ,  Yun-Tae Lee ,  Sung-Man Hwang

IPC: G11C29/04 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G11B20/00086

Abstract: A flash memory system includes a flash memory for storing input data, and a memory controller controlling the flash memory, wherein the memory controller generates a first error correction code corresponding to the input data, and encrypts the first error correction code, and the flash memory includes a main area for storing the input data and a spare area for storing the encrypted first error correction code.

Abstract translation: 闪速存储器系统包括用于存储输入数据的闪速存储器和控制闪速存储器的存储器控​​制器，其中存储器控制器产生对应于输入数据的第一纠错码，并对第一纠错码进行加密，并且闪速存储器 包括用于存储输入数据的主区域和用于存储加密的第一纠错码的备用区域。

公开(公告)号：US20080163023A1

公开(公告)日：2008-07-03

申请号：US11785719

申请日：2007-04-19

Applicant: Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

Inventor： Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

IPC: H03M13/00

CPC classification number: H03M13/2945 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/136 ,  H03M13/1505 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/29 ,  H03M13/2906

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

Abstract translation: 存储M位数据（M为等于或大于2的正整数）的闪速存储器件的ECC（纠错码）控制器包括从程序数据生成第一ECC数据的第一ECC块， 根据第一纠错方法存储在闪速存储装置中的第二ECC数据和根据第二纠错方法从第一ECC数据和从第一ECC块输出的程序数据生成第二ECC数据的第二ECC块， ，第一ECC数据和第二ECC数据被存储在闪存设备中。

公开(公告)号：US20070136536A1

公开(公告)日：2007-06-14

申请号：US11553201

申请日：2006-10-26

Applicant: Sung-Jae Byun ,  Young Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

Inventor： Sung-Jae Byun ,  Young Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

IPC: G06F9/00 ,  G06F12/00 ,  G06F15/177

CPC classification number: G06F12/0607 ,  G06F9/4405 ,  G06F15/177 ,  G11C8/16 ,  Y02D10/13

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract translation: 多处理器系统包括第一处理器，与第一处理器通信的第二处理器，用于存储第一代码和第二代码以分别引导第一和第二处理器的第一非易失性存储器，可与第一处理器通信的第一存储器， 为第一处理器指定的第二易失性存储器，为第二处理器指定的第三易失性存储器，以及由第一和第二处理器共享的第四易失性存储器。

公开(公告)号：US20050144492A1

公开(公告)日：2005-06-30

申请号：US11023331

申请日：2004-12-27

Applicant: Byeong-Whee Yun ,  Yun-Tae Lee

Inventor： Byeong-Whee Yun ,  Yun-Tae Lee

IPC: G06F1/04 ,  G06F1/30 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/305 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: A processor system power voltage has low idle level as compared to a normal level during an idle mode. Power consumption of the processor during the idle mode is reduced. A power voltage supplied to the processor is increased to a normal level in returning to a normal mode from the idle mode, and a frequency of a clock signal supplied to the processor is decreased in comparison with a normal frequency. As a result, it is possible to prevent misoperation of the processor.

Abstract translation: 在空闲模式期间，处理器系统电源电压与正常电平相比具有低空闲电平。 在空闲模式期间处理器的功耗降低。 提供给处理器的电源电压在从空闲模式返回到正常模式时增加到正常电平，并且提供给处理器的时钟信号的频率与正常频率相比降低。 结果，可以防止处理器的误操作。

公开(公告)号：US07725746B2

公开(公告)日：2010-05-25

申请号：US11747774

申请日：2007-05-11

Applicant: Jin-aeon Lee ,  Yun-tae Lee

Inventor： Jin-aeon Lee ,  Yun-tae Lee

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F9/00

CPC classification number: G06F1/3228 ,  G06F1/3243 ,  G06F1/3246 ,  Y02D10/152 ,  Y02D50/20

Abstract: Provided are an apparatus and method of transmitting working context, which can minimize power consumption in a power-off standby mode of a portable apparatus including a system on a chip, where the method includes selecting a power-off standby mode, transmitting working context with respect to a hardware module, which is mounted on a semiconductor chip, to a predetermined memory, and storing the working context in the predetermined memory, transmitting the working context stored in the memory to a non-volatile memory outside the semiconductor chip, and storing the working context in the non-volatile memory, and executing the power-off standby mode; where the method may further include releasing the power-off standby mode, restoring the working context with respect to the hardware module, which is stored in the non-volatile memory, to the predetermined memory, and recovering the at least one hardware module to a state existing immediately before the power-off standby mode was executed by using the working context restored to the memory from the non-volatile memory.

Abstract translation: 提供了一种发送工作环境的装置和方法，其可以使包括芯片上的系统的便携式设备的断电待机模式中的功率消耗最小化，其中该方法包括选择断电待机模式， 将安装在半导体芯片上的硬件模块相对于预定存储器，并将工作上下文存储在预定存储器中，将存储在存储器中的工作上下文传送到半导体芯片外部的非易失性存储器，并存储 非易失性存储器中的工作环境，以及执行掉电待机模式; 其中所述方法还可以包括释放所述断电待机模式，将存储在所述非易失性存储器中的所述硬件模块的工作上下文恢复到所述预定存储器，以及将所述至少一个硬件模块恢复到 在通过使用从非易失性存储器恢复到存储器的工作上下文执行关闭待机模式之前存在的状态。

公开(公告)号：US07594126B2

公开(公告)日：2009-09-22

申请号：US11023331

申请日：2004-12-27

Applicant: Byeong-Whee Yun ,  Yun-Tae Lee

Inventor： Byeong-Whee Yun ,  Yun-Tae Lee

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/305 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: A processor system power voltage has low idle level as compared to a normal level during an idle mode. Power consumption of the processor during the idle mode is reduced. A power voltage supplied to the processor is increased to a normal level in returning to a normal mode from the idle mode, and a frequency of a clock signal supplied to the processor is decreased in comparison with a normal frequency. As a result, it is possible to prevent misoperation of the processor.

Abstract translation: 在空闲模式期间，处理器系统电源电压与正常电平相比具有低空闲电平。 在空闲模式期间处理器的功耗降低。 提供给处理器的电源电压在从空闲模式返回到正常模式时增加到正常电平，并且提供给处理器的时钟信号的频率与正常频率相比降低。 结果，可以防止处理器的误操作。

公开(公告)号：US07155556B2

公开(公告)日：2006-12-26

申请号：US10883943

申请日：2004-07-02

Applicant: Young-Jun Kim ,  Jin-Aeon Lee ,  Yun-Tae Lee

Inventor： Young-Jun Kim ,  Jin-Aeon Lee ,  Yun-Tae Lee

IPC: G06F13/00

CPC classification number: G06F13/404 ,  G06F2213/0038

Abstract: A host integrated circuit device can include a host interface circuit that is configured to access a resource associated with the host integrated circuit device in a first device interface format based on a request from a remote integrated circuit device located outside the host integrated circuit device in a second device interface format.

Abstract translation: 主机集成电路装置可以包括主机接口电路，其被配置为基于来自位于主机集成电路装置外部的远程集成电路装置的请求以第一装置接口格式访问与主机集成电路装置相关联的资源 第二设备接口格式。