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公开(公告)号：KR1020040090816A
公开(公告)日：2004-10-27
申请号：KR1020030024780
申请日：2003-04-18
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L29/4238 , H01L23/4824 , H01L29/41758 , H01L29/78 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A transistor capable of reducing gate capacitance is provided to reduce the resistance of a gate electrode of a transistor by making the gate electrode formed of a mesh type and by forming an isolation layer in the crossing point of the gate electrode. CONSTITUTION: A semiconductor substrate(200) is prepared. An active region(205) is formed in a predetermined portion of the semiconductor substrate. The gate electrode(220) is formed on the semiconductor substrate by interposing a gate insulation layer, formed of a mesh type composed of a plurality of bar patterns that extend in the lengthwise direction and the widthwise direction. A source/drain region(235a,235b) is formed in the active region at both sides of the gate electrode. An isolation layer(210a,210b) is formed in the active region, overlapping the crossing part of the gate electrode of the mesh type.
Abstract translation: 目的：提供一种能够减小栅极电容的晶体管，通过使栅电极形成为网状，并通过在栅电极的交叉点形成隔离层来降低晶体管的栅电极的电阻。 构成：制备半导体衬底（200）。 在半导体衬底的预定部分中形成有源区（205）。 栅电极（220）通过插入由多个沿长度方向和宽度方向延伸的棒状图案的网状形成的栅极绝缘层而形成在半导体基板上。 源极/漏极区域（235a，235b）形成在栅电极两侧的有源区域中。 隔离层（210a，210b）形成在有源区域中，与网状栅极栅极的交叉部分重叠。
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公开(公告)号：KR100074446B1
公开(公告)日：1994-06-14
申请号：KR1019910007496
申请日：1991-05-09
Applicant: 삼성전자주식회사
IPC: H01L21/304
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公开(公告)号：KR1019940001152B1
公开(公告)日：1994-02-14
申请号：KR1019910007496
申请日：1991-05-09
Applicant: 삼성전자주식회사
IPC: H01L21/304
Abstract: An oxide layer is formed on the surface of the substrate by vapor deposition method, after sequentially, forming an oxide layer, N+ sinker, a gate and an intrinsic base region. All regions except bipolar region, is dry-etched to give the side wall spacer after dopping the oxide layer of bipolar region with photoresist. By ion implantation N+ source/drain electrode is formed, and P+ source/drain electrode and the intrinsic base region are formed. An emitter region is etched after vapor-depositing the oxide layer on the whole surface of the substrate, and then N+ poly is deposited and etched.
Abstract translation: 在基板的表面上通过气相沉积法形成氧化物层，依次形成氧化物层，N +沉降片，栅极和本征基极区域。 除双极区域之外的所有区域被干蚀刻，以在用光致抗蚀剂掺杂双极区域的氧化物层之后得到侧壁间隔物。 通过离子注入形成N +源极/漏极，形成P +源极/漏极和本征基极区。 在衬底的整个表面上气相沉积氧化物层之后蚀刻发射极区域，然后沉积和蚀刻N +聚合物。
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公开(公告)号：KR1019930006128B1
公开(公告)日：1993-07-07
申请号：KR1019910001861
申请日：1991-01-31
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76897 , H01L21/76885 , H01L2924/0002 , H01L2924/00
Abstract: The method for forming a metal wire is characterized by (a) forming a contact hole on a first insulating film formed on the semiconductor substrate, (b) forming a first metal layer on the whole surface, (c) forming a half of a first metal wire, (d) forming a side wall spacer of a second insulating layer on the side surface of the first metal layer, and then etching the first insulating film, (e) forming a second metal layer on the whole surface, and (f) etching a second metal layer, and then forming a half of a first metal wire.
Abstract translation: 形成金属线的方法的特征在于：（a）在形成于半导体基板上的第一绝缘膜上形成接触孔，（b）在整个表面上形成第一金属层，（c）形成第一 金属线，（d）在第一金属层的侧面上形成第二绝缘层的侧壁隔离物，然后蚀刻第一绝缘膜，（e）在整个表面上形成第二金属层，（f ）蚀刻第二金属层，然后形成第一金属线的一半。
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Patent Agency Ranking
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公开(公告)号：KR100870178B1
公开(公告)日：2008-11-25
申请号：KR1020050073498
申请日：2005-08-10
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
Abstract: 엠아이엠 커패시터를 갖는 반도체 소자들이 제공된다. 상기 반도체 소자들은 칩 영역 및 상기 칩 영역에 인접한 스크라이브 레인 영역을 갖는 반도체 기판을 구비한다. 상기 반도체 기판 상에 하부 층간절연막이 적층되고, 상기 칩 영역의 상기 하부 층간절연막 내에 하부 배선이 제공된다. 상기 하부 배선 및 상기 하부 층간절연막은 하부 캐핑 절연막으로 덮여지고, 상기 칩 영역의 상기 하부 캐핑 절연막 상에 하부 금속전극이 제공된다. 상기 하부 금속전극은 상기 하부 캐핑 절연막을 관통하는 콘택홀을 통하여 상기 하부배선에 전기적으로 접속된다. 상기 하부 금속전극 상에 유전체막 패턴이 적층되고, 상기 유전체막 패턴의 일 부분 상에 상부 금속전극이 제공된다. 상기 엠아이엠 커패시터의 제조방법 또한 제공된다.
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公开(公告)号：KR1020080100078A
公开(公告)日：2008-11-14
申请号：KR1020070046191
申请日：2007-05-11
Applicant: 삼성전자주식회사
Inventor： 이덕민
IPC: G11C11/4074
CPC classification number: G05F3/16 , G11C11/4074 , H03K5/133
Abstract: A high speed operation of the bias generating circuit is provided to shorten the operation time of bias voltage outputted to each bias voltage terminal when a bias generating circuit is started up. In a bias generating circuit, a first current path or the sixth current path are connected between the power supply voltage and reference voltage(I1-I6). A first gate line(G1) controls the first current path or the third current path and is connected to the first current path. A second gate line(G2) which is connected to the second current path controls the first current path, the second current path, and fourth current path. A third gate line(G3) controls the fourth current path and the fifth current path while being connected to the fourth current path, outputs the first bias voltage(Vb1) corresponding to the current flowing in the fourth current path. A coupling capacitor(C1) couples the third gate line to the first gate line. A first transient capacitor(C2) is connected between the power supply voltage and the first gate line.
Abstract translation: 提供偏置产生电路的高速操作以缩短当偏置产生电路启动时输出到每个偏置电压端子的偏置电压的操作时间。 在偏置发生电路中，第一电流路径或第六电流路径连接在电源电压和参考电压（I1-I6）之间。 第一栅极线（G1）控制第一电流路径或第三电流路径并连接到第一电流路径。 连接到第二电流路径的第二栅极线（G2）控制第一电流路径，第二电流路径和第四电流路径。 第三栅极线（G3）在连接到第四电流路径的同时控制第四电流路径和第五电流路径，输出与在第四电流路径中流动的电流对应的第一偏置电压（Vb1）。 耦合电容器（C1）将第三栅极线耦合到第一栅极线。 第一瞬态电容器（C2）连接在电源电压和第一栅极线之间。
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公开(公告)号：KR100784872B1
公开(公告)日：2007-12-14
申请号：KR1020060075248
申请日：2006-08-09
Applicant: 삼성전자주식회사
IPC: H01L27/146
CPC classification number: H01L27/14689 , H01L27/1461 , H01L27/14614 , H01L29/6656
Abstract: An image sensor and a fabricating method thereof are provided to prevent a short-channel effect by ensuring a width of a channel region, and prevent a surface of a light receiving element from being damaged at an etching process. A transfer gate(130a) is formed on an active region defined in a substrate(110). A first insulating layer(141) and a second insulating layer(142) are formed on the substrate. Impurity ions are implanted on the substrate to form a light receiving device(112) in the active region at one side of the transfer gate and a floating diffusion region(115) in the active region at the other side of the transfer gate. A first spacer layer and a second spacer layer are formed on the second insulating layer. A spacer(155a) is formed on both sidewalls of the transfer gate.
Abstract translation: 提供了一种图像传感器及其制造方法，以通过确保沟道区域的宽度来防止短沟道效应，并且防止光接收元件的表面在蚀刻处理中被损坏。 传输门（130a）形成在限定在衬底（110）中的有源区上。 在基板上形成第一绝缘层（141）和第二绝缘层（142）。 将杂质离子注入到衬底上以在传输栅极的一侧的有源区域中形成光接收器件（112），并且在传输栅极的另一侧的有源区域中形成浮动扩散区域（115）。 在第二绝缘层上形成第一间隔层和第二间隔层。 间隔物（155a）形成在传输门的两侧壁上。
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