公开(公告)号：KR101331019B1

公开(公告)日：2013-11-19

申请号：KR1020070005392

申请日：2007-01-17

Applicant: 삼성전자주식회사

Inventor： 김선영 ,  황홍기

IPC: G06F9/24 ,  G06F1/24

Abstract: 부팅시스템이 개시된다. 본 발명의 부팅 시스템은 핀 리셋 신호의 입력이 인식되면 내부 리셋 신호를 출력하는 리셋부, 리셋부로부터 내부 리셋신호가 수신되면, CLE 신호를 출력하는 컨트롤러, 및 핀 리셋 신호 및 CLE 신호를 논리 연산하여, 그 연산 결과에 따라 CLE 신호를 메모리로 전달하는 연산부를 포함한다. 이에 따라, 리셋부의 오동작으로 인한 부팅수행을 방지할 수 있게 된다.
부팅시스템, CLE, AND게이트, 리셋신호.

公开(公告)号：KR1020080032878A

公开(公告)日：2008-04-16

申请号：KR1020060098957

申请日：2006-10-11

Applicant: 삼성전자주식회사

Inventor： 황홍기 ,  김선영

IPC: G11C7/10 ,  G11C8/12

Abstract: A memory access device and a method thereof are provided to prevent frequent arbitration on a system bus and to increase data transmission efficiency, by transmitting data not corresponding to a burst unit in a burst unit. A slave(130) writes and reads data. A master(110) transmits the data to the slave. The master divides and transmits the data in a burst unit constituted with a fixed number of bits, and adds a random value to the residual data in order to correspond to the burst unit, when smaller data than the burst unit remains. The master further transmits a burst mask signal indicating whether each data transmitted in the burst unit is valid data or invalid data.

Abstract translation: 提供了一种存储器访问装置及其方法，用于通过在突发单元中发送不对应于突发单元的数据来防止系统总线上的频繁仲裁并提高数据传输效率。 从机（130）写入和读取数据。 主机（110）将数据发送到从机。 主要以固定数量的比特构成的突发单元划分并发送数据，并且当与突发单元相比较小的数据保留时，为了对应于突发单元，向残差数据添加随机值。 主机还发送突发掩码信号，指示在突发单元中发送的每个数据是有效数据还是无效数据。

公开(公告)号：KR1020080032781A

公开(公告)日：2008-04-16

申请号：KR1020060098725

申请日：2006-10-11

Applicant: 삼성전자주식회사

Inventor： 황홍기 ,  김선영

IPC: G06F13/14 ,  G06F13/38 ,  G06F13/36

Abstract: A bus arbitration system is provided to improve performance requested to each master by adjusting an access waiting time of a slave to a bus, the master, or the slave based on a priority determination mode like a run level priority and a cycle priority. Primary slaves(340-1~340-3) process data received from a master. Secondary slaves(390-1~390-3) receive/process the data processed in the primary slaves. A bus unit(360) connects the primary slaves and the secondary slaves. A slave arbiter(350) assigns bus use for connecting to the primary slaves to the secondary slaves through a second bus(380). First buses(320-1~320-n) are connected to masters(311-1~311-n,313-1~313-n). A bus matrix(330) switches connection between the bus and the primary slaves. The bus unit includes the second bus connected to the secondary slaves, and a multiplexer(370) connecting the primary slaves and the second bus according to a bus use state assigned from the slave arbiter. The slave arbiter determines priority according to a run level by receiving the run level corresponding to importance of data transfer from the masters and assigns the bus use according to the determined priority.

Abstract translation: 提供总线仲裁系统以通过基于诸如运行级别优先级和循环优先级的优先级确定模式来调整从站到总线，主站或从站的访问等待时间来改善对每个主站所请求的性能。 主从站（340-1〜340-3）处理从主站接收的数据。 辅助从站（390-1〜390-3）接收/处理主从站中处理的数据。 总线单元（360）连接主从站和从站。 从属仲裁器（350）通过第二总线（380）分配总线用于连接到主从机到次从机。 第一条总线（320-1〜320-n）连接主机（311-1〜311-n，313-1〜313-n）。 总线矩阵（330）切换总线和主从站之间的连接。 总线单元包括连接到次从站的第二总线，以及根据从从仲裁器分配的总线使用状态连接主从设备和第二总线的多路复用器（370）。 从属仲裁器通过接收与主机的数据传输的重要性相对应的运行电平，根据运行级别确定优先级，并根据确定的优先级分配总线使用。

公开(公告)号：KR1020070033181A

公开(公告)日：2007-03-26

申请号：KR1020050087613

申请日：2005-09-21

Applicant: 삼성전자주식회사

Inventor： 황홍기

IPC: H03K3/012 ,  H03L7/08

CPC classification number: G06F1/324 ,  G06F1/04 ,  H03B5/32 ,  H03L7/0805

Abstract: A clock generating apparatus and a method thereof are provided to generate a frequency lower than a standard input frequency of a clock source by dividing a compensating operation clock frequency to drive a system and compensating for the clock. In a clock generating apparatus, a frequency divider(100) generates a standard input clock frequency of a clock source. A clock generator(200) generates an operation clock frequency by tuning and varying a frequency of the standard input clock frequency. The operation clock frequency drives a system. The clock generator(200) generates a clock having a frequency lower than the standard input clock frequency by dividing the operation clock frequency. An output determining part(400) outputs the generated clock after dividing the operation clock frequency in a power save mode of the system. The output determining part(400) outputs the operation clock as a clock source in a normal operation mode.

Abstract translation: 提供了一种时钟发生装置及其方法，通过对补偿操作时钟频率进行分频来产生比时钟源的标准输入频率低的频率，以驱动系统并补偿时钟。 在时钟发生装置中，分频器（100）产生时钟源的标准输入时钟频率。 时钟发生器（200）通过调谐和改变标准输入时钟频率的频率来产生操作时钟频率。 操作时钟频率驱动系统。 时钟发生器（200）通过划分操作时钟频率来产生具有低于标准输入时钟频率的频率的时钟。 输出确定部分（400）在系统的省电模式中分配操作时钟频率之后输出生成的时钟。 输出判定部（400）在正常运行模式下将运算时钟作为时钟源输出。

公开(公告)号：KR1020070010366A

公开(公告)日：2007-01-24

申请号：KR1020050064879

申请日：2005-07-18

Applicant: 삼성전자주식회사

Inventor： 황홍기

IPC: G03G15/00

CPC classification number: G03G15/5004 ,  G03G15/80

Abstract: A low-power analog/digital conversion system of an image forming apparatus and a method of detecting a system error are provided to detect an error generated when an analog/digital converter is operated, automatically restore the analog/digital converter to a normal state, and vary a clock cycle for each channel to reduce power consumption. A low-power analog/digital conversion system of an image forming apparatus includes a controller(200). The controller automatically initializes the system so as to restore the system to a normal state when an analog/digital output value transmitted through at least one channel and converted into a digital value is deviated from a predetermined reference range, an analog/digital average value sampled by a predetermined number of times for each channel is out of a predetermined reference range, or an analog/digital conversion completion signal periodically generated in response to an analog/digital conversion clock signal is not generated within a predetermined period of time.

Abstract translation: 提供图像形成装置的低功率模拟/数字转换系统和检测系统误差的方法来检测模拟/数字转换器工作时产生的错误，自动将模拟/数字转换器恢复到正常状态， 并改变每个通道的时钟周期以降低功耗。 图像形成装置的低功率模拟/数字转换系统包括控制器（200）。 当通过至少一个通道传输并转换成数字值的模拟/数字输出值偏离预定参考范围时，控制器自动初始化系统，以便将系统恢复到正常状态，模拟/数字平均值采样 每个通道的预定次数不在预定的参考范围内，或者在预定时间段内不产生响应于模拟/数字转换时钟信号周期性地产生的模拟/数字转换完成信号。

公开(公告)号：KR1020060040156A

公开(公告)日：2006-05-10

申请号：KR1020040089385

申请日：2004-11-04

Applicant: 삼성전자주식회사

Inventor： 황홍기

IPC: G06F9/38

CPC classification number: G06F9/38

Abstract: 복수의 채널을 가진 DMA컨트롤러에서 Bulk DMA동작이 가능한 정보처리장치 및 그 Bulk DMA동작방법이 개시된다. 본 정보처리장치는 인쇄대상 데이터가 저장되는 메모리, 메모리의 액세스 횟수를 카운트하여, 기설정된 액세스 횟수와 동일하면, 타이머틱을 발생하는 타이머, 및 메모리에 액세스하여, 연결된 복수의 채널 중 기설정된 우선순위 채널로 인쇄대상 데이터가 입출력되도록 메모리를 제어하고, 타이머에서 타이머틱이 발생되면 연결된 복수의 채널 중 기설정된 다음 우선순위 채널로 변경하여 인쇄대상 데이터가 입출력되도록 메모리를 제어하는 DMA제어부를 구비한다. 이에 의해, 메모리나 SFR에 저장되어 있는 DCB리스트를 한꺼번에 읽어오는 시간만 소요되므로, DMA 동작 처리 시간이 감소될뿐만 아니라, 전체 성능이 향상되는 이점이 있다.
DMA, 다중채널, Bulk