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公开(公告)号：KR1019940017582A
公开(公告)日：1994-07-27
申请号：KR1019920026062
申请日：1992-12-29
IPC: H04M3/22
Abstract: 본 발명은 대용량 전전자 교환시스템에서의 제어시스템의 이중화 운용 방법에 관한 것이다.
본 발명은 교환 시스템의 고도의 고장 감내 기능을 구현함과 함께 이의 실현에 있어서 필수인 성능저하를 최소로 하고, 동시에 최소한의 소프트웨어 부담으로 데이타의 일치성 및 장애 발생시 빠른 재구성과(reconfiguration)과 재시동(recovery)을 갖는 제어시스템의 이중화 운영방법을 제공한다.-
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公开(公告)号：KR1019930007466B1
公开(公告)日：1993-08-11
申请号：KR1019900022875
申请日：1990-12-31
IPC: H04M3/22
Abstract: This invention relates to a method of equalizing the memory of each processors in a dualized large scale full electronic switching system. This method comprises the 1st stage at which stand-by processor (abbreviation D) demands the memory copy and working D connects D-channel and demands address, the 2nd stage at which whether to copy is determined, the 3rd stage at which the memory is equalized and D sleeps, the 4th stage at which control is passed over to the 2nd stage, and the 5th stage at which whether the control is passed over is determined or the dummy D is activated.
Abstract translation: 本发明涉及一种均衡二进制大规模全电子交换系统中每个处理器的存储器的方法。 该方法包括第一级，待机处理器（缩写D）要求存储器复制，工作D连接D信道并要求地址，第二级确定是否复制，第三级存储器是 均衡D睡眠，第四阶段控制转到第二阶段，第五阶段确定控制是否通过，否则虚拟D被激活。
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Patent Agency Ranking
公开(公告)号：KR1019950012316B1
公开(公告)日：1995-10-16
申请号：KR1019920026132
申请日：1992-12-29
Applicant: 한국전자통신연구원
IPC: H04L12/02
Abstract: The method comprises the steps of applying a discriminating element after determining processors to be tested through an IPC message; determining the pairs of the processor; starting the test by means of the network control processor and performing a real test; returning to the second step if the test is more required; and extending the detected data to the total system if the test is not needed any more and maintaining the data.
Abstract translation: 该方法包括以下步骤：通过IPC消息确定要测试的处理器之后应用鉴别元件; 确定处理器的对; 通过网络控制处理器开始测试并进行实际测试; 如果测试更需要，返回第二步; 并且如果不再需要测试并维护数据，则将检测到的数据扩展到总系统。
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公开(公告)号：KR1019930007465B1
公开(公告)日：1993-08-11
申请号：KR1019900022874
申请日：1990-12-31
IPC: H04M3/22
Abstract: The object of this invention is to solve the difficulties of conventional techniques and to provide more stable and fast direct communication method between dualized processors. This invention comprises the 1st stage at which messages and checksum are saved in temporary registers and written in identification registers, the 2nd stage at which a transmitter waits for the arrival acknowledgement signal, the 3rd stage at which the receiver checks interrupts and checksums, the 4th stage at which the receiver copies messages in the ID registers, the 5th stage at which the receiver checks the transmission and the 6th stage at which the transmitter demands a retrial.
Abstract translation: 本发明的目的是解决常规技术的困难，并且在二元化处理器之间提供更稳定和快速的直接通信方法。 本发明包括将消息和校验和保存在临时寄存器中并写入识别寄存器的第一阶段，发送机等待到达确认信号的第二阶段，接收机检查中断的第三阶段和校验和，第四阶段 接收器在ID寄存器中复制消息的阶段，接收机检查传输的第五阶段和发射机要求重试的第六阶段。
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公开(公告)号：KR1019930007464B1
公开(公告)日：1993-08-11
申请号：KR1019900022873
申请日：1990-12-31
IPC: H04M3/22
Abstract: The method for switching the operating system in the duplicated processor based electronic switching system comprises: a processor unit (PU,1) consisting a main board and a memory management board; a communication control board (5,PCCA) to control communication between both system; a duplication switching control board (6,DCCA) to control D-channel (7) and C-channel, where the D-channel (7) is for the processor synchronization and C- channel (8) for the communication path. The switching method could be operated by manually or automatically upon the proper operating condition.
Abstract translation: 用于在基于重复处理器的电子交换系统中切换操作系统的方法包括：包括主板和存储器管理板的处理器单元（PU，1） 通信控制板（5，PCCA），用于控制两个系统之间的通信; 复用切换控制板（6，DCCA），用于控制D信道（7）和C信道，其中D信道（7）用于处理器同步，C信道（8）用于通信路径。 切换方式可以在适当的运行条件下手动或自动运行。
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