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11.发明公开
公开(公告)号：KR1020080050302A
公开(公告)日：2008-06-05
申请号：KR1020070105753
申请日：2007-10-19
Applicant: 한국전자통신연구원
CPC classification number: H04Q11/0066 , H04L47/10
Abstract: A method of detecting an effective frame length for preventing a fragment loss in an EPON(Ethernet Passive Optical Network) MAC(Media Access Control) is provided to manage plural reference values for plural Ethernet frame buffers by using a minimum sized frame length memory of an ONU(Optical Network Unit). A reference value for a size of data to be transmitted is set in a frame buffer. A remaining frame length, which corresponds to a difference between a sum of input Ethernet frame lengths and a smallest reference value of the reference values greater than the sum of the lengths, is obtained. When the length of a new Ethernet frame is smaller than the remaining frame length, a sum of the previous Ethernet frame lengths is detected as an effective frame length. Otherwise, the sum of the previous Ethernet frame lengths and the sum of the new Ethernet frame lengths are detected as the effective frame lengths.
Abstract translation: 提供了一种用于防止EPON（以太网无源光网络）MAC（媒体访问控制）中的片段丢失的有效帧长度检测方法，用于通过使用最小尺寸的帧长度存储器来管理多个以太网帧缓冲器的多个参考值 ONU（光网络单元）。 要发送的数据的大小的参考值被设置在帧缓冲器中。 获得对应于输入以太网帧长度的总和和大于长度之和的参考值的最小参考值之间的差的剩余帧长度。 当新的以太网帧的长度小于剩余的帧长度时，先前的以太网帧长度之和被检测为有效的帧长度。 否则，检测以前的以太网帧长度和新的以太网帧长度之和作为有效帧长度。
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公开(公告)号：KR1020070059821A
公开(公告)日：2007-06-12
申请号：KR1020060027117
申请日：2006-03-24
Applicant: 한국전자통신연구원
Abstract: A method for managing service bandwidths according to customers and an EPON(Ethernet Passive Optical Network) system using the same are provided to perform customer management more definitely and execute service bandwidth control more diversely and minutely according to customers and service types by classifying customer access ports by customers. Customer identifiers are allocated according to each customer(S10). Service identifiers are allocated according to each of service types and features(S20). Service priorities are allocated according to service features(S30). Service classes are determined by combinations of customer identifiers, service identifiers, and service priorities(S40). Permissible service bandwidths are established according to the service classes(S50). Bandwidth control is carried out according to the service classes(S60).
Abstract translation: 提供一种根据客户管理服务带宽的方法和使用该方法的EPON（以太网无源光网络）系统，更加明确地执行客户管理，并根据客户和服务类型，通过对客户接入端口进行分类，更加多样化，细致地执行服务带宽控制 由客户 客户标识符根据每个客户分配（S10）。 服务标识符根据服务类型和特征分配（S20）。 服务优先级根据业务特征分配（S30）。 服务类别通过客户标识符，服务标识符和服务优先级的组合来确定（S40）。 根据服务等级建立允许的业务带宽（S50）。 根据服务等级进行带宽控制（S60）。
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公开(公告)号：KR100462471B1
公开(公告)日：2004-12-17
申请号：KR1020020053451
申请日：2002-09-05
Applicant: 한국전자통신연구원
CPC classification number: H04L27/0014 , H04L2025/03375 , H04L2025/0349 , H04L2027/0055
Abstract: A method and apparatus for compensating for phase errors of a digital signal are provided. An equalizer compensates for an amplitude distortion of a received signal caused by a channel and outputs an equalized signal after a first predetermined delay time elapses. A first multiplying means complex multiplies the equalized signal by a phase corrected signal and outputs a first multiplied value. A first multiplexing means selectively outputs either the received signal or the first multiplied value based upon whether the first predetermined time has elapsed. A phase compensating means sets an initial value of a local oscillator based upon an average value of phase errors of the received signal before the first predetermined time elapses, and removes phase errors existing in the first multiplied value after the first predetermined time elapses.
Abstract translation: 提供了一种用于补偿数字信号的相位误差的方法和装置。 均衡器补偿由信道引起的接收信号的幅度失真，并在经过第一预定延迟时间之后输出均衡信号。 第一乘法装置复数将均衡信号乘以相位校正信号并输出第一相乘值。 第一多路复用装置根据第一预定时间是否已经过去，有选择地输出接收信号或第一相乘值。 相位补偿装置根据在经过第一预定时间之前接收信号的相位误差的平均值来设置本机振荡器的初始值，并且在经过第一预定时间之后去除存在于第一相乘值中的相位误差。
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公开(公告)号：KR100450759B1
公开(公告)日：2004-10-01
申请号：KR1020020004420
申请日：2002-01-25
Applicant: 한국전자통신연구원
IPC: H04L12/20
CPC classification number: H04L49/9094 , H04L49/90
Abstract: A method for transmitting and receiving leased line data, an apparatus for transmitting leased line data, and an apparatus for receiving leased line data are provided. The method includes storing received leased line data in a FIFO; packing the leased line date stored in the FIFO into the payload of a DSL frame; and transmitting the packed DSL frame. According to the method, leased line data can be transparently transmitted by adding minimum function blocks to the DSL modem, and with the simple circuit structure, the blocks can be integrated into one chip such that no additional external circuits are needed and a low-priced DSL modem chip that can transmit leased line data can be implemented.
Abstract translation: 提供了一种用于发送和接收租用线路数据的方法，一种用于发送租用线路数据的装置以及一种用于接收租用线路数据的装置。 该方法包括将接收到的租用线路数据存储在FIFO中; 将存储在FIFO中的专线日期打包到DSL帧的有效载荷中; 并传输打包的DSL帧。 根据该方法，可以通过向DSL调制解调器添加最小功能块来透明地传输租用线路数据，并且通过简单的电路结构，块可以被集成到一个芯片中，从而不需要额外的外部电路，并且低价 可以实现可以传输租用线路数据的DSL调制解调器芯片。
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公开(公告)号：KR1020040022308A
公开(公告)日：2004-03-12
申请号：KR1020020053451
申请日：2002-09-05
Applicant: 한국전자통신연구원
CPC classification number: H04L27/0014 , H04L2025/03375 , H04L2025/0349 , H04L2027/0055
Abstract: PURPOSE: A device of compensating for a phase error of a digital signal is provided to stop an operation of an equalizer during delay time of the equalizer, and to operate the equalizer after almost removing a phase error, thereby enabling the equalizer to focus on removing inter-symbol interference by reducing burden of the equalizer. CONSTITUTION: An equalizer(210) outputs a compensated equalization signal when the first predetermined delay time elapses. The first multiplier(260) complex-multiplies the compensated signal, and outputs the first multiplied value. The first multiplexer(220) selectively outputs a receiving signal and the first multiplied value. A phase compensator(230) sets an initial value of a local oscillator before the first delay time elapses, and removes a phase error existing in the first multiplied value after the first delay time elapses. A signal decider(240) decides an original signal from an inputted signal. A subtractor(290) compares an input signal with an output signal, and detects an error. The second multiplier(270) multiplies the output signal of the subtractor(290) by an output signal of the phase compensator(230), and outputs the second multiplied value. The third multiplier(280) multiplies an output signal of the decider(240) by the output signal of the compensator(230), and outputs the third multiplied value. The first switch(295-1) supplies an output signal of the first multiplexer(220) to the subtractor(290). The second switch(295-2) supplies the output signal of the decider(240) to the subtractor(290) and the third multiplier(280). An error controller(250) controls an error value, and supplies the error value to the equalizer(210).
Abstract translation: 目的：提供补偿数字信号的相位误差的装置，以在均衡器的延迟时间期间停止均衡器的操作，并且在几乎消除相位误差之后操作均衡器，从而使均衡器能够集中于去除 符号间干扰减轻均衡器的负担。 构成：当第一预定延迟时间过去时，均衡器（210）输出经补偿的均衡信号。 第一乘法器（260）对补偿信号进行复乘，并输出第一相乘值。 第一复用器（220）选择性地输出接收信号和第一相乘值。 相位补偿器（230）在第一延迟时间经过之前设置本地振荡器的初始值，并且在经过第一延迟时间之后去除存在于第一相乘值中的相位误差。 信号判定器（240）根据输入信号判定原始信号。 减法器（290）将输入信号与输出信号进行比较，并检测错误。 第二乘法器（270）将减法器（290）的输出信号乘以相位补偿器（230）的输出信号，并输出第二相乘值。 第三乘法器（280）将判决器（240）的输出信号乘以补偿器（230）的输出信号，并输出第三乘法值。 第一开关（295-1）将第一多路复用器（220）的输出信号提供给减法器（290）。 第二开关（295-2）将决定器（240）的输出信号提供给减法器（290）和第三乘法器（280）。 误差控制器（250）控制误差值，并将误差值提供给均衡器（210）。
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Patent Agency Ranking
公开(公告)号：KR1020030090307A
公开(公告)日：2003-11-28
申请号：KR1020020028362
申请日：2002-05-22
Applicant: 한국전자통신연구원
IPC: H04B7/005
CPC classification number: H04L25/03019
Abstract: PURPOSE: A scalable adaptive equalizer is provided to flexibly control the number of tap blocks and prevent overflow generated from tap coefficient. CONSTITUTION: A feed-forward filter(101) filters a signal inputted through a predetermined transmission line for generating a compensated signal reduced an influence of the transmission line. A tap coefficient adjusting unit(102) generates a tap coefficient adjusting signal obtained by multiplying a signal obtained by subtracting a feedback signal from the compensated signal by a predetermined tap coefficient adjusting constant. A deciding unit(103) receives the tap coefficient adjusting signal for generating a symbol signal and an error signal corresponding to a difference between the symbol signal and a target symbol signal. A feedback filter(104) receives the symbol signal and the error signal for generating a feedback signal corresponding to an interference value to the current symbol by an adjacent symbol of the inputted signal.
Abstract translation: 目的：提供可扩展的自适应均衡器，以灵活地控制抽头数量，并防止抽头系数产生的溢出。 构成：前馈滤波器（101）对通过预定传输线输入的信号进行滤波，以产生补偿信号，减少了传输线的影响。 抽头系数调整单元（102）产生通过将从补偿信号减去反馈信号而获得的信号乘以预定抽头系数调整常数而获得的抽头系数调整信号。 决定单元（103）接收用于产生符号信号的抽头系数调整信号和对应于符号信号和目标符号信号之间的差的误差信号。 反馈滤波器（104）接收符号信号和误差信号，用于通过输入信号的相邻符号产生对应于当前符号的干扰值的反馈信号。
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公开(公告)号：KR100402785B1
公开(公告)日：2003-10-22
申请号：KR1020000083307
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: H04L27/34
CPC classification number: H04L27/3494 , H04L1/0002
Abstract: A variable-rate QAM (Quadrature Amplitude Modulation) transceiver of the present invention facilitates data interfacing between a number of bands having different transmission rates by using a number of transmitters and receivers in downstream and upstream, respectively, to provide a symmetric service in which data transmission rate in upstream is equal to that in downstream even under environment of serious channel attenuation of a signal for high frequency. That is, the variable-rate QAM transceiver of the present invention comprises a number of transmitter blocks for providing various transmission rates to the transmitters and a number of receiver blocks for providing various transmission rates to the receivers, for properly adjusting bandwidth allocation of the passband signal bandwidth of a number of transmitters and receivers to enable high speed symmetric data transmission.
Abstract translation: 本发明的可变速率QAM（正交幅度调制）收发机通过分别使用下游和上游的多个发射机和接收机来促进具有不同传输速率的多个频带之间的数据接口，以提供对称服务，其中数据 即使在高频信号信道衰减严重的环境下，上行传输速率也与下行传输速率相同。 也就是说，本发明的可变速率QAM收发器包括用于向发射器提供各种传输速率的多个发射器块和用于向接收器提供各种传输速率的多个接收器块，用于适当地调节通带的带宽分配 多个发射机和接收机的信号带宽以实现高速对称数据传输。
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公开(公告)号：KR100315430B1
公开(公告)日：2001-11-26
申请号：KR1019990061933
申请日：1999-12-24
Applicant: 한국전자통신연구원
IPC: H04L27/01
Abstract: 본발명은멀티캐리어변복조시스템에서의주파수영역등화장치에관한것으로, 멀티캐리어변복조시스템에서의모든부채널에대한주파수영역등화를반복하여수행하기위한등화장치를제공하기위하여, 각부채널별심볼값과상기각 부채널별로보정해주어야할 위상정보인고정된값을읽어와곱하며곱해진값을주파수영역등화기의초기값으로사용하여상기부채널별로등화를수행하기위한복소적응등화수단; 상기고정된값을상기각 부채널별로읽고저장하기위한제 1 저장수단; 상기제 1 저장수단으로부터상기각 부채널별데이터를읽고, 상기각 부채널별탭값을상기제 1 저장수단에쓰기위한수를발생하기위한어드레스카운팅수단; 푸리에변환된각 부채널별심볼값을저장하는제 2 저장수단; 및상기어드레스카운팅수단의카운트값에따라상기제 2 저장수단으로부터해당하는부채널심볼을선택하여상기복소적응등화수단으로전달하기위한스위칭수단을포함하며, 멀티캐리어변복조시스템등에이용됨.
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公开(公告)号：KR1020010064257A
公开(公告)日：2001-07-09
申请号：KR1019990062407
申请日：1999-12-27
Applicant: 한국전자통신연구원
IPC: H04L29/00
Abstract: PURPOSE: A high performance software modem platform board is provided which has an additional analog front end and digital interface to be able to serve as a modem directly and realizes a variety of modem functions within a short period of time by replacing only the analog front end. CONSTITUTION: A software modem platform board includes an analog front end for filtering an input analog signal to convert the signal into a digital signal in case of reception and converting data into an analog signal to transmit the signal through an analog filter, and the first field programmable gate array(FPGA) for performing pre-processing using clock recovery, frame clock recovery and adapted filter for the digital signal and pulse-shaping input transmission data. The platform board further has the second and third FPGAs for transmitting input data to an upper layer and carrying out an error correction pre-processing to send data transmitted from the upper layer, the first, second and third serial ROMs for storing a user program which will be downloaded to the first, second and third FPGAs, and the first, second and third digital signal processors(DSPs) for executing various operation processes for received data and carrying out IFFT for transmission data. The platform board also has a flash ROM for storing user data, a synchronous burst SRAM and synchronous DRAM for storing intermediate operation results, and a CPLD for controlling the devices and boards. Complex operations are allocated to the DSPs and simple high-speed operations and bit operations are assigned to the FPGAs to maximize operation efficiency.
Abstract translation: 目的：提供高性能软件调制解调器平台板，其具有额外的模拟前端和数字接口，能够直接用作调制解调器，并在短时间内实现各种调制解调器功能，只需将模拟前端 。 构成：软件调制解调器平板电路板包括模拟前端，用于过滤输入模拟信号，以在接收时将信号转换为数字信号，并将数据转换为模拟信号，以通过模拟滤波器传输信号，第一场 可编程门阵列（FPGA），用于使用时钟恢复进行预处理，帧时钟恢复和适用于数字信号和脉冲整形输入传输数据的滤波器。 平台板还具有用于将输入数据发送到上层的第二和第三FPGA，并执行纠错预处理以发送从上层发送的数据，第一，第二和第三串行ROM，用于存储用户程序， 将被下载到第一，第二和第三FPGA，以及第一，第二和第三数字信号处理器（DSP），用于对接收的数据执行各种操作处理并且执行用于传输数据的IFFT。 平台板还具有用于存储用户数据的闪存ROM，用于存储中间操作结果的同步突发SRAM和同步DRAM，以及用于控制设备和板的CPLD。 复杂的操作被分配给DSP，并且简单的高速操作和位操作被分配给FPGA以最大化操作效率。
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