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公开(公告)号：KR101235376B1
公开(公告)日：2013-02-21
申请号：KR1020090027976
申请日：2009-04-01
Applicant: 한국전자통신연구원
Abstract: 본 발명은 이더넷 링 보호 절체 방법 및 시스템에 관한 것으로서, 이더넷 하위 계층 장애 신호인 SSF(Server Signal Fail), 단방향 장애 발생시 다른 쪽 포트로 장애 상태를 알리기 위한 신호인 RDI(Remote Defect Indication) 및 이더넷 링 보호 절체를 요청하기 위한 R-APS(Ring-Automatic Protection Switching) 정보를 수신하는 단계; 상기 SSF, 상기 RDI 및 상기 R-APS 정보를 비교한 후, 상기 제1, 제2 이더넷 링의 상태를 설정하는 단계; 상기 제1, 제2 이더넷 링의 상태에 따라 이더넷 링의 보호 절체 우선순위를 결정하는 단계; 및 상기 이더넷 링의 보호 절체 우선순위에 따라 상기 제1, 제2 이더넷 링을 보호 절체하는 단계를 포함한다.
이더넷 링, 보호 절체, 우선 순위, 상태 정보-
公开(公告)号：KR1020110088391A
公开(公告)日：2011-08-03
申请号：KR1020110004710
申请日：2011-01-17
Applicant: 한국전자통신연구원
IPC: H04L12/24
CPC classification number: H04L49/557 , H04L45/22
Abstract: PURPOSE: A linear protection switching method is provided to allocate a protection path as a high priority working path. CONSTITUTION: Based on a priority rank of a working path and a second working path, a first node(501) locates a bridge and a selector which uses a protection path. The node 1 transmits a first failure message. A node 2(502) creates a second failure message. The first node allocates the second bridge and the second selector of traffic as a protection path.
Abstract translation: 目的：提供一种线性保护切换方法，将保护路径分配为高优先级的工作路径。 构成：基于工作路径和第二工作路径的优先等级，第一节点（501）定位使用保护路径的网桥和选择器。 节点1发送第一失败消息。 节点2（502）创建第二个故障消息。 第一节点分配第二个桥和第二个流量选择器作为保护路径。
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公开(公告)号：KR100922725B1
公开(公告)日：2009-10-22
申请号：KR1020070053481
申请日：2007-05-31
Applicant: 한국전자통신연구원
Abstract: 본 발명에 의한 이더넷 링크 이중화 장치 및 그 방법은 각각 이중화된 물리매체, 이더넷 물리계층장치 및 이더넷 MAC 계층장치를 포함하는 이더넷 이중화 링크를 가지며 이더넷 이중화 링크 중 하나는 운용링크로, 나머지 하나는 운용링크의 예비링크로 사용하는 이더넷 링크 이중화 장치에 있어서, 상대방 이더넷 링크 이중화 장치와 이더넷 데이터를 송수신하는 운용링크 상에 위치한 이더넷 물리계층장치의 상태정보를 인식하여, 이더넷 물리계층장치의 상태정보를 기초로 로컬 상태정보를 생성하는 로컬 이더넷 물리계층 시그널링부, 로컬 상태정보의 생성을 인지하고, 생성된 로컬 상태 정보를 전달하는 로컬 이더넷 MAC 계층 시그널링부 및 로컬 상태정보를 기초로, 문제가 발생한 운용링크를 기 설정된 운용링크의 예비링크로 절체하는 로컬 링크절체부를 가진다. 본 발명은 물리계층의 상태정보 시그널링 및 이더넷 이중화 링크를 활용하여 추가적인 상위 계층의 시그널링 없이 간단하고 효율적인 링크 보호 절체를 수행하는 이더넷 링크 이중화 장치 및 그 방법을 제공한다.
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公开(公告)号：KR1020080039189A
公开(公告)日：2008-05-07
申请号：KR1020070053481
申请日：2007-05-31
Applicant: 한국전자통신연구원
CPC classification number: H04L1/22 , H04L12/12 , H04L41/0668 , H04L69/323
Abstract: An Ethernet link duplication apparatus using a state information signaling in an Ethernet physical layer, and a method thereof are provided to perform a simple and efficient link protection switch without an additional upper layer signaling by using a state information signaling and Ethernet link duplication in a physical layer. An Ethernet link duplication apparatus using a state information signaling in an Ethernet physical layer includes a local Ethernet physical layer signaling unit(120-1), a local Ethernet MAC(Medial Access Control)(121-1), and a local link switch unit(108). The local Ethernet physical layer signaling unit recognizes state information of the Ethernet physical layer device which is located on an operation link for transceiving Ethernet data with the other Ethernet link duplication device, and generates local state information based on the state information of the Ethernet physical layer device. The local Ethernet MAC layer signaling unit recognizes a generation of the local state information, and transfers the generated local state information. The local link switch unit switches an operation link having a problem into a predetermined preliminary link based on the local state information.
Abstract translation: 在以太网物理层中使用状态信息信令的以太网链路复制装置及其方法被提供以通过使用物理上的状态信息信令和以太网链路复制来执行简单而有效的链路保护交换机，而不需要额外的上层信令 层。 在以太网物理层中使用状态信息信令的以太网链路复制装置包括本地以太网物理层信令单元（120-1），本地以太网MAC（中访问控制）（121-1）和本地链路交换单元 （108）。 本地以太网物理层信令单元识别位于用于与其他以太网链路复制设备收发以太网数据的操作链路上的以太网物理层设备的状态信息，并且基于以太网物理层的状态信息生成本地状态信息 设备。 本地以太网MAC层信令单元识别出本地状态信息的生成，并传送所生成的本地状态信息。 本地链路切换单元基于本地状态信息将具有问题的操作链路切换到预定的初步链路。
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公开(公告)号：KR1020070061049A
公开(公告)日：2007-06-13
申请号：KR1020060037213
申请日：2006-04-25
Applicant: 한국전자통신연구원
IPC: H03L7/085
CPC classification number: H03L7/0891 , H03L7/0816 , H03L7/095 , H03L7/18
Abstract: A phase lock detecting apparatus is provided not to affect operation of a phase synchronizing circuit by using a reference signal and a feedback signal instead of using an internal signal of the phase synchronizing circuit. A phase lock detecting apparatus includes a variable delaying unit(10), a control signal generating unit(12), and a phase lock detecting unit(14). The variable delaying unit generates a delay reference signal by delaying a reference signal in response to a control signal. The control signal generating unit compares phases of the delay reference signal and the feedback signal, and generates the control signal including information that the phase of the delay reference signal exceeds the feedback signal by a predetermined critical value, and information that the phase of the feedback signal exceeds the delay reference signal by the predetermined critical value. The phase lock detecting unit(14) detects a phase lock based on the control signal.
Abstract translation: 通过使用参考信号和反馈信号而不使用相位同步电路的内部信号，提供锁相检测装置不影响相位同步电路的操作。 锁相检测装置包括可变延迟单元（10），控制信号生成单元（12）和锁相检测单元（14）。 可变延迟单元通过响应于控制信号延迟参考信号来产生延迟参考信号。 控制信号生成单元比较延迟参考信号和反馈信号的相位，并产生包括延迟参考信号的相位超过反馈信号预定临界值的信息的控制信号，以及反馈信号的相位 信号超过延迟参考信号预定的临界值。 相位锁定检测单元（14）基于控制信号检测相位锁定。
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Patent Agency Ranking
公开(公告)号：KR1020050048423A
公开(公告)日：2005-05-24
申请号：KR1020030082348
申请日：2003-11-19
Applicant: 한국전자통신연구원
IPC: H04B3/04
CPC classification number: H04L25/03343
Abstract: 본 발명은 수신측의 전송 특성에 따라 적응화된 등화 및 프리엠퍼시스를 수행하는 데이터 송수신 장치 및 방법에 관한 것으로, 상기 데이터 송수신 장치는 전송 선로를 통과하여 입력되는 데이터 신호로부터 전송 선로의 신호 감쇄 특성을 파악하여 왜곡된 입력 데이터의 파형을 복원하고, 데이터 수신시 파악된 전송 선로의 신호 감쇄 특성을 이용하여 송신 데이터 신호의 파형을 미리 변형시켜 출력함으로써 출력되는 데이터 신호가 전송 선로를 통과한 후에 이상적인 파형을 유지하도록 한다.
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公开(公告)号：KR1020030080502A
公开(公告)日：2003-10-17
申请号：KR1020020019167
申请日：2002-04-09
IPC: H04L7/00
Abstract: PURPOSE: A multi link data recovery and retiming apparatus using a multi phase clock is provided, which enables a stable operation by assuring a constant timing margin. CONSTITUTION: A phase comparison unit(100) outputs N phase comparison result signals by receiving input data(Din) and N multiple phase clock signals synchronized to the input data. A delay compensation unit(200) receives the input data and the multiple phase clock signals, and outputs data arranged to the multiple phase clock signals by retiming the input data. And a buffering buffer unit(300) recovers the input data by assembling the retimed data to a reference bit clock signal optimally by receiving the multiple phase clock signals and the phase comparison result signals and the data arranged to the multiple phase clock signals and the reference bit clock signal.
Abstract translation: 目的：提供使用多相时钟的多链路数据恢复和重新定时装置，通过确保恒定的时间裕度来实现稳定的操作。 构成：相位比较单元（100）通过接收与输入数据同步的输入数据（Din）和N个多相位时钟信号来输出N相比较结果信号。 延迟补偿单元（200）接收输入数据和多相位时钟信号，并通过重新定时输入数据来输出配置到多相时钟信号的数据。 并且缓冲缓冲单元（300）通过接收多相时钟信号和相位比较结果信号以及布置到多相时钟信号和参考的数据来最优地组合重定时数据到参考位时钟信号来恢复输入数据 位时钟信号。
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公开(公告)号：KR100392817B1
公开(公告)日：2003-07-28
申请号：KR1020010047498
申请日：2001-08-07
IPC: H04L12/44
Abstract: PURPOSE: A parallel demultiplexing system for mass switching and a method therefor are provided to perform a high-speed mass communication by connecting cells as a tree structure, distributing each cell to a sub-path in parallel using a tree traversal method, inserting a link for indicating a sub-path of a next cell into a header of the cell, transmitting the cell through a plurality of sub-paths, and reassembling the cell in parallel. CONSTITUTION: A parallel cell distributing unit(210) segments inputted data into a plurality of cells, connects a plurality of cells as an M-way tree in which a leader cell is root, and distributes each cell to sub-paths in parallel using a certain tree traversal method. The parallel cell distributing unit(210) inserts a link for indicating a sub-path of a next transmission cell into a header of the cell, and transmits each cell to the sub-path. A parallel cell assembly unit(220) stores the cell transmitted from each sub-path in a cell queue according to sub-paths, analyzes the link inserted into the header of each cell, reassembles the cell in parallel according to the analyzed result, and transmits the reassembled cell.
Abstract translation: 目的：提供了一种用于批量切换的并行解复用系统及其方法，用于通过将单元连接为树结构来执行高速大量通信，使用树遍历方法将每个单元并行分配到子路径，插入链路 用于将下一个小区的子路径指示到小区的报头中，通过多个子路径发送该小区，并且并行地重组该小区。 组成：并行信元分配单元（210）将输入的数据分割成多个信元，将多个信元作为以引导信元为根的M路树连接，并将每个信元并行地分配给子路径，使用 某种树遍历方法。 并行信元分配单元（210）将用于指示下一个传输信元的子信道的链路插入信元的信头中，并且将每个信元传送到子信道。 并行信元组装单元（220）根据子路径将从每个子路径发送的信元存储在信元队列中，分析插入到每个信元的信头中的链路，根据分析结果并行地重组该信元，以及 传输重组的小区。
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公开(公告)号：KR1020030013158A
公开(公告)日：2003-02-14
申请号：KR1020010047498
申请日：2001-08-07
IPC: H04L12/44
Abstract: PURPOSE: A parallel demultiplexing system for mass switching and a method therefor are provided to perform a high-speed mass communication by connecting cells as a tree structure, distributing each cell to a sub-path in parallel using a tree traversal method, inserting a link for indicating a sub-path of a next cell into a header of the cell, transmitting the cell through a plurality of sub-paths, and reassembling the cell in parallel. CONSTITUTION: A parallel cell distributing unit(210) segments inputted data into a plurality of cells, connects a plurality of cells as an M-way tree in which a leader cell is root, and distributes each cell to sub-paths in parallel using a certain tree traversal method. The parallel cell distributing unit(210) inserts a link for indicating a sub-path of a next transmission cell into a header of the cell, and transmits each cell to the sub-path. A parallel cell assembly unit(220) stores the cell transmitted from each sub-path in a cell queue according to sub-paths, analyzes the link inserted into the header of each cell, reassembles the cell in parallel according to the analyzed result, and transmits the reassembled cell.
Abstract translation: 目的：提供用于质量切换的并行解复用系统及其方法，用于通过将小区连接为树结构来执行高速大规模通信，使用树遍历方法将每个小区并行地分配到子路径，插入链路 用于将下一个小区的子路径指示到小区的头部，通过多个子路径发送小区，并且并行重新组合小区。 构成：并行单元分配单元（210）将输入的数据分割成多个单元，将多个单元作为前导单元为根的M方向树连接，并且将每个单元并行地分配给子路径 某些树遍历方法。 并行单元分配单元（210）将用于指示下一个传输小区的子路径的链路插入到小区的首部，并将每个小区发送到子路径。 并行单元组合单元（220）根据子路径将从每个子路径发送的小区存储在小区队列中，分析插入每个小区的报头中的链路，根据分析结果并行重新组合小区，以及 传输重新组装的单元。
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公开(公告)号：KR1020010009727A
公开(公告)日：2001-02-05
申请号：KR1019990028262
申请日：1999-07-13
IPC: H03B5/14
Abstract: PURPOSE: A two-stage ring voltage controlling oscillator by using a couple of variable delay elements is provided to carry out the function as a voltage controlling oscillator even if accuracy, security and reappearance in the manufacturing progress aren't outstanding. CONSTITUTION: A two-stage ring voltage controlling oscillator by using a couple of variable delay elements includes the first analog mixer(321), the fist variable delay element portion(33), the first, M-delay or reversing element(323), the second, M-delay or reversing element(322), the second analog mixer(331), the second variable delay element portion(33), the second M-delay or reversing element(333) and the second, first delay or reversing element(332). In the first analog mixer(321) of the fist variable delay element portion(33) inputs the output of the first, M-delay or reversing element(323) and output of the second, M-delay or reversing element(322) and mixes them with analog and outputs them with the input of the first, first delay or reversing element(322). The first, first delay or reversing element(322) and the first, M-delay or reversing element(323) generate the delayed or reversed signal with adding the amplitude of the input signal. The second analog mixer(331) of the second variable delay element portion(33) inputs the output of the second M-delay or reversing element(333) and output of the second, M-delay or reversing element(332) and mixes them with analog and outputs them with the input of the second, first delay or reversing element(332). The second, first delay or reversing element(322) and the second, M-delay or reversing element(333) generate the delayed or reversed signal with adding the amplitude of the input signal.
Abstract translation: 目的：提供使用两个可变延迟元件的两级环形电压控制振荡器，即使在制造进度中的准确性，安全性和再现性不突出的情况下也能够实现作为电压控制振荡器的功能。 构成：通过使用一对可变延迟元件的两级环形电压控制振荡器包括第一模拟混频器（321），第一可变延迟元件部分（33），第一M延迟或反向元件（323）， 第二M延迟或反转元件（322），第二模拟混频器（331），第二可变延迟元件部分（33），第二M延迟或反转元件（333）和第二延迟或反转元件 元件（332）。 在第一可变延迟元件部分（33）的第一模拟混合器（321）中，输入第一M延迟或反向元件（323）的输出和第二M延迟或反向元件（322）的输出和 将它们与模拟混合并输出它们与第一，第一延迟或反向元件（322）的输入。 第一，第一延迟或反向元件（322）和第一M延迟或反向元件（323）通过增加输入信号的幅度产生延迟或反转的信号。 第二可变延迟元件部分（33）的第二模拟混合器（331）输入第二M延迟或反向元件（333）的输出和第二M延迟或反向元件（332）的输出并将它们混合 并具有第二，第一延迟或反向元件（332）的输入。 第二，第一延迟或反向元件（322）和第二M延迟或反向元件（333）通过增加输入信号的幅度产生延迟或反转的信号。
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