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公开(公告)号：KR1019960007677B1
公开(公告)日：1996-06-08
申请号：KR1019930008511
申请日：1993-05-18
IPC: H04L12/433
Abstract: The device for discriminating synchronous transfer mode cell boundary using a 5-byte syndrome generator includes: a HEC (Header Error Control) decoding means 10 for generating the syndrome for successive 5 byte data from byte data streams based on a syndrome load signal and a syndrome reset signal and an external input data, extracting the cell boundary, and correcting a single bit error in the cell header; an HEC state tracing means 30 for checking whether a mode set signal provided from the HEC decoding means 10 is in a tracing state, a semi-synchronous state, or a synchronous state; and an HEC driving means 20, for providing the syndrome load signal and the syndrome reset signal, providing the mode signal to the HEC state tracing means 30 and having a plurality of bits error detection, the HEC mode detection, an effective cell transferring functions.
Abstract translation: 用于使用5字节校正子发生器鉴别同步传输模式信元边界的装置包括：HEC（报头错误控制）解码装置10，用于基于综合征负载信号和综合征产生来自字节数据流的连续5字节数据的校正子 复位信号和外部输入数据，提取单元边界，以及校正单元首标中的单个位错误; 用于检查从HEC解码装置10提供的模式设置信号是否处于跟踪状态，半同步状态或同步状态的HEC状态跟踪装置30; 以及HEC驱动装置20，用于提供综合征负载信号和校正子复位信号，向HEC状态跟踪装置30提供模式信号，并具有多个位错误检测，HEC模式检测，有效的小区传送功能。
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公开(公告)号：KR1019960012841A
公开(公告)日：1996-04-20
申请号：KR1019940024375
申请日：1994-09-27
IPC: H04L12/433
Abstract: 본 발명은 전용 방송 버스 구조를 갖는 소규모 출력 버퍼형 ATM 스위칭 장치에서 주요 기능 처리부인 출력 처리부의 구성을 두단계 버퍼링 방법과 속도 이득 방법 및 입력셀들의 동기/비동기 상태에 무관하게 동작하는 방법을 이용하여 입력 포트수가 16이하인 소규모 출력 버퍼형 ATM 스위칭 장치를 장치 구성에 소요되는 버퍼수의 절감효과 및 버스트 트래픽 처리 기능이 우수하고 내부 제어가 간단하도록 구성한 출력 버퍼형 에이.티.엠(ATM)스위칭 장치에 관한것으로, 일반적인 출력 버퍼형 스위칭 장치보다 소요 버퍼의 축소 효과를 제공하면서,기존의 넉 아웃 스위칭 장치는 제어 방식기 갖는 장점보다는 장치의 구성이 상대적으로 복잡하나 본 발명은 장치의 용량이 16이하인 소규모일 경우로 한정하여 보다 장치의 구성을 단순화시키면서도 한 출력 접 속부로 셀이 동시에 몰리는 트래픽에 대한 처리 특성을 강화시킨다.
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14.发明授权비동기식 전송 모드 시스템에서 물리계층수신부의 실시간 섹션 오버헤드 바이트 검출 및 발생을 위한 장치 및 방법 失效用于异步传输模式系统中物理层接收机中的实时部分开销字节检测和生成的设备和方法
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公开(公告)号：KR1019960003224B1
公开(公告)日：1996-03-07
申请号：KR1019920024195
申请日：1992-12-14
IPC: H04L12/28
Abstract: a transmitting cell matching part having an ATM cell transmitting block which buffers a cell transmitted from an ATM hierarchy to output the buffered cell according to a control signal, an OAM(operation and maintenance) cell transmitting block which buffers an OAM cell transmitted from a physical hierarchical managing unit to output the buffered cell according to the control signal, an idle cell generating block which transmits an idle cell if the ATM cell and the OAM cell do not exist, and a multiplexor which mulitiplexes the ATM cell, the OAM cell, and the idle cell in accordance with the control signals from a transmitting cell matching part control block; and a receiving cell matching part having a receiving cell dividing block which divides types of receiving cells, a receiving cell matching part control block which controls an overall function of a receiving part, an OAM cell receiving block which stores the divided OAM cell to transmit the cell to the physical hierarchical managing unit, and an ATM cell receiving block which stores the divided ATM cell to transmit the cell to the ATM hierarchy.
Abstract translation: 具有ATM信元发送块的发送小区匹配部，其缓冲从ATM层次发送的小区，根据控制信号输出被缓存的小区; OAM（运营和维护）小区发送块，其缓冲从物理上发送的OAM小区 分级管理单元，根据控制信号输出缓冲单元，空闲单元生成块，如果ATM单元和OAM单元不存在则发送空闲单元;多路复用器，其将ATM单元，OAM单元和 所述空闲小区根据来自发送小区匹配部分控制块的控制信号; 以及具有分割接收单元的类型的接收单元划分块的接收单元匹配单元，控制接收单元的整体功能的接收单元匹配单元控制单元，存储分割后的OAM单元的OAM单元接收单元， 单元到物理分层管理单元，以及ATM信元接收块，其存储分割的ATM信元以将该信元发送到ATM层级。
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Patent Agency Ranking
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公开(公告)号：KR1019960001055B1
公开(公告)日：1996-01-17
申请号：KR1019930018156
申请日：1993-09-09
IPC: H04L12/00
Abstract: a slot discriminator for discriminating an activated slot from an effective slot, the activated slot having an effective cell information from an input cell slot, and the effective slot not having the effective cell information; a pre-input/output unit for selectively outputting a buffering when a service holding signal is inputted through an input of the cell slots discriminated from the slot discriminator; an off section recognizing unit for recognizing an off section between the number of effective slots of the slot discriminator, and for finding out a start point of a burst; a burst length observing unit for counting the length of the burst from the start point of the burst under use of an off section signal from the off section recognition unit and an active slot signal from slot discriminator, comparing the length of the burst with the maximum length of a determined burst, and outputting a maximum burst length disobedience signal during disobedience; and a service holding unit for generating a service holding signal when the maximum burst length disobedience signal is sensed from the burst length observing unit, and buffering the cell slots inputted to a selective buffering pre-input/output unit.
Abstract translation: 用于鉴别激活的时隙与有效时隙的时隙鉴别器，所述激活时隙具有来自输入小区时隙的有效小区信息，所述有效时隙不具有有效小区信息; 预输入/输出单元，用于当通过从时隙鉴别器识别的信元时隙的输入来输入服务保持信号时，选择性地输出缓冲; 断开识别单元，用于识别所述时隙鉴别器的有效时隙数量之间的断开部分，并且用于发现突发的起始点; 一个突发长度观察单元，用于从使用来自截断识别单元的截止信号的脉冲串起始点和来自时隙鉴别器的有效时隙信号对从脉冲串起始点开始的脉冲串的长度进行计数，将脉冲串的长度与最大值 确定突发的长度，并且在不服从期间输出最大突发长度不服从信号; 以及服务保持单元，用于当从所述突发长度观察单元感测到所述最大突发长度不服从信号时，生成服务保持信号，以及缓存输入到选择性缓冲预输入/输出单元的小区时隙。
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公开(公告)号：KR1019950012327B1
公开(公告)日：1995-10-16
申请号：KR1019920026118
申请日：1992-12-29
IPC: H04L12/28
Abstract: The apparatus and method is for detecting real time overhead byte of STM-1 frame. The apparatus includes a 3-phase signal generator(21) for generating signals needed to BIP24 calculation, a position signal generator(22) for generating enable signals for special bytes(B2,Z2) in section overhead bytes, and an overhead generator(23) for executing BIP24 calculation, for generating a section overhead byte(Z2), and for storing whole overhead.
Abstract translation: 该装置和方法用于检测STM-1帧的实时开销字节。 该装置包括用于产生BIP24计算所需的信号的三相信号发生器（21），用于在部分开销字节中产生用于特殊字节（B2，Z2）的使能信号的位置信号发生器（22）和一个架空发生器 ），用于执行BIP24计算，用于生成段开销字节（Z2），并用于存储整个开销。
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公开(公告)号：KR1019950009417B1
公开(公告)日：1995-08-22
申请号：KR1019920024187
申请日：1992-12-14
IPC: H04L12/28
Abstract: an information input and state definition means which selects and presents priority data by receiving state information of each input buffer and by receiving priority information of each input presented by ATM layer controller ; a control signal generating means which controlls the output of cell generator or each input buffer of cell multiplication part by comparing the priority data selected at the information input and state definition means.
Abstract translation: 信息输入和状态定义装置，通过接收每个输入缓冲器的状态信息并通过接收由ATM层控制器呈现的每个输入的优先级信息来选择和呈现优先级数据; 控制信号发生装置，通过比较在信息输入和状态定义装置中选择的优先级数据来控制单元发生器或单元乘法部分的每个输入缓冲器的输出。
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公开(公告)号：KR1019950009416B1
公开(公告)日：1995-08-22
申请号：KR1019920024186
申请日：1992-12-14
IPC: H04L12/28
Abstract: The multiplexer comprises an input cell receiving unit for inputting a protocol cell data provided from a service data, i.e., ATM cell, and a layer controlling part, storing the cell data inputted to a corresponding connection point of an input buffer, and outputting state information of each input buffer, which is differently shown according to feature of the input cell data; an idle/non-assignment cell generating unit for generating a spare cell and a non-assignment cell in order to fill a cell stream of a bite unit corresponding to a STM-1 frame format and a transmission format of a cell environment when the data is not accumulated in the input buffer; a cell multiple controlling unit for inputting a specific information of the input data provided from the ATM layer controlling part and a state information outputted from the input cell receiving unit, and outputting one of control signals to be used for selecting either the cell data to be multiplexed, or the idle/non-assignment cell data; and a cell multiplexing unit inputting the control signal from the cell multiple controlling unit, and outputting multplexing data by abstracting the cell data of the input cell receiving unit and the idle/non-assignment cell data from the cell stream of the bite unit.
Abstract translation: 多路复用器包括：输入单元接收单元，用于输入从服务数据提供的协议单元数据，即ATM单元，以及层控制单元，存储输入到输入缓冲器的对应连接点的单元数据，并输出状态信息 每个输入缓冲器根据输入单元数据的特征不同地显示; 一个空闲/非分配单元产生单元，用于产生备用单元和非分配单元，以填充对应于STM-1帧格式的单元单元流和单元环境的传输格式，当数据 未在输入缓冲器中累积; 用于输入从ATM层控制部分提供的输入数据的特定信息和从输入单元接收单元输出的状态信息的单元多重控制单元，并输出要用于选择单元数据的控制信号之一 多路复用，或空闲/非分配单元数据; 以及单元多路复用单元，其输入来自单元多个控制单元的控制信号，并且通过从所述咬合单元的单元流抽出所述输入单元接收单元的单元数据和所述空闲/非分配单元数据来输出多路复用数据。
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