Abstract:
An FFT(Fast Fourier Transform) device for increasing a data processing capacity and a method thereof are provided to increase an FFT processing capacity without increasing hardware by installing and using additional memories in a time-division mode. First and second memory banks(330,340) store input data, and alternatively store FFT processed data. A data processor(370) performs FFT of the input data stored in the first and second memory banks. A first multiplexer(310) selects the input data and the processed data of the data processor alternatively depending on a selection control signal, and stores the selected data to the first memory bank. A second multiplexer(320) selects the input data and the processed data of the data processor alternatively depending on the selection control signal, and stores the selected data to the second memory bank. A third multiplexer(350) selects the input data stored in the first and second memory banks alternatively depending on the selection control signal, and transfers the selected data to the data processor. A fourth multiplexer(360) outputs the processed data stored in the first and second memory banks alternatively depending on the selection control signal. A controller outputs the selection control signal to the multiplexers.
Abstract:
물리 채널이 복수의 시간 영역의 심볼과 복수의 주파수 영역의 부반송파의 조합으로 이루어져 있는 통신 시스템의 송신 장치는 데이터를 복수의 데이터 블록으로 분할한 후에 복수의 데이터 블록을 각각 인터리빙한다. 그리고 나서, 인터리빙된 복수의 데이터 블록을 적어도 하나의 물리 채널에 매핑하여 통신 시스템의 수신 장치로 전송한다. 이와 같이 하면, 데이터 인터리빙에 따른 시간 지연을 감소시킬 수 있다. 부반송파, 심볼, 물리 채널, 트랜스포트 채널, 매핑, 인터리빙
Abstract:
An apparatus and a method for generating preamble and an apparatus and a method for detecting a channel response are provided to reduce hardware and a processing time by generating the preamble by using an interpolator and detecting the channel response by using a decimator. A sequence generation part generates a frequency sequence including a plurality of factors in a frequency domain(S110). An IDFT operating part performs an IDFT(Inverse Discrete Fourier Transform) of the frequency sequence generated by the sequence generation part and produces the inverse Fourier transform signal(S120). A protective interval insertion part inserts the protective interval into the inverse Fourier transform signal and produces the protective interval insertion signal(S130). An interpolator performs the interpolation of the protective interval insertion signal and produces an RA preamble(S140). The frequency band of the RA preamble which the interpolator produces is positioned in the base band. A frequency hopping part produces frequency hopped RA preamble by moving the RA preamble of the base band to the frequency band to be transmitted(S150). A transmission part transmits the frequency-hopped RA preamble which the frequency hopping part produces to the channel response detecting device through the channel(S160).
Abstract:
A method for configuring a QAM(Quadrature Amplitude Modulation) constellation with hexagonal determination areas and a coded modulation apparatus using the same are provided to reduce an SER(Symbol Error Rate) by increasing the minimum distance between constellation points in comparison with a conventional square constellation. In a method for configuring a QAM constellation with hexagonal determination areas, the hexagonal determination areas with constellation points at the center are arranged according to the modulation order. The hexagonal determination areas are sequentially surrounded around a central point. The minimum distance between the constellation points is maintained equally and the average transmission energy is reduced by using the hexagonal determination area.
Abstract:
본 발명은 상향링크 수신단의 유효비트 제어에 적합한 자동 이득 제어 장치 및 그 방법에 관한 것이다. 본 발명에서는 기지국의 수신단에서 수신되는 상향링크 신호의 첫 번째 CP와 심볼의 평균 전력을 측정하여 해당 프레임의 이득 제어를 수행한다. 이득 제어를 위한 평균 전력 측정시 해당 CP와 심볼은 버퍼 내에 저장되고, 버퍼의 출력은 수신 모듈로 출력되지 않도록 경로 제어된다. 전력 측정부는 이득 제어기에서 출력되는 하나의 CP와 심볼에 대해 평균 전력을 측정하며, 측정된 평균 전력의 값에 해당하는 이득 제어 계수를 결정하여 이득 제어기의 이득을 제어한다. 이 때, 서브프레임이 상향링크 채널 추정용 심볼을 전송하는 경우에는 이득 제어 계수를 데이터 심볼만 전송하는 경우에 비해 작게 설정하여 이득 제어기에 의해 선택되는 유효 비트의 수가 작도록 제어한다. 그리고, 첫 번째 데이터 심볼에 대해서 다시 평균 전력을 측정하여 이득 제어를 수행한다. 본 발명에 따르면, 프레임 단위로 실시간 유효 비트를 변경시키면 기지국의 전력 제어에 의한 단말 송신 전력 제어시, 기지국 수신단에 기지국 수신 모듈에서 제어 할 수 있는 입력 비트 레벨을 넘는 경우 올 수 있는 성능 열화를 감쇠시킬 수 있다. 이득 제어, 상향링크, 이득 제어 계수, AGC, ADC
Abstract:
프리앰블 생성 장치는 주파수 영역에서 시퀀스를 생성하고, 시퀀스를 푸리에 역변환하여 시간 영역에서 푸리에 역변환 신호를 생성하며, 푸리에 역변환 신호를 인터폴레이션하여 프리앰블을 생성한다. 이를 통해 큰 크기의 DFT/IDFT를 사용하지 않고 프리앰블을 생성할 수 있다. 프리앰블, 채널, 응답
Abstract:
A method and an apparatus for acquiring synchronization of a multi-antenna in an orthogonal frequency division multiple access system are provided to obtain initial synchronization in a terminal having the multi-antenna by searching symbol timing from signals inputted from a terminal to the multi-antenna. An apparatus for acquiring synchronization of a multi-antenna in an orthogonal frequency division multiple access system comprises a signal combiner, an initial symbol timing estimator, a frame detector, a frequency offset estimator, and a timing synchronizer. The signal combiner combines each signal inputted to the multi-antenna. The initial symbol timing estimator estimates initial symbol timing and a fractional multiplicative frequency offset using the combined signal. The frame detector detects a frame starting point based on the estimated value. The frequency offset estimator estimates a frequency offset based on the frame starting point. The timing synchronizer searches symbol timing by compensating the frequency offset.
Abstract:
A DFT(double Fourier Transform) device and a method thereof are provided to realize a DFT operation through hardware in a field needing DFT for data not a multiplier of two, reduce a memory by reading data from a buffer and storing the data to the buffer, and reduce latency and increase throughout by reducing an interval between input and output for the DFT. A buffer(200) stores data and a single stage unit(300) generates FT data by performing the FT for the data stored in the buffer. An entire stage controller(100) enables the buffer to store the data, forms a plurality of single stages respectively corresponding to a plurality of even numbers factorizing a resource unit of the data, and controls the FT by using the single stage unit for a plurality of single stage. The entire stage controller is equipped with an even number former(101) including entire stage structure information including the number and the order of single stages corresponding to a plurality of even numbers, and the even number of each single stage, and controls the single stage according to the entire stage structure information for the data stored in the even number former.
Abstract:
A resource allocation method in an SC-FDMA(Single Carrier Frequency Division Multiple Access) communication system for efficient channel estimation and a device are provided to use pilots which are adjacent to all subcarriers allocated to one user for channel estimation even without increasing a PAPR(Peak-to-Average Power Ratio), thereby improving accuracy in channel estimation. Symbols to be sent by a user are divided into at least two groups(S610). DFT(Discrete Fourier Transform) processes are performed for the symbols according to each group to generate DFT data(S620). During resource allocation in long blocks through a distributive method for the DFT data, DFT data of the same sequence of each group are individually allocated to long blocks having neighboring subcarriers(S630). Pilots for the user channel estimation are allocated to short blocks adjacent to the long blocks having the neighboring subcarriers(S640).