公开(公告)号：EP2862202B1

公开(公告)日：2016-04-27

申请号：EP13729005.2

申请日：2013-06-06

Applicant: ABB Technology AG

Inventor： HARTMANN, Samuel ,  TRÜSSEL, Dominik

IPC: H01L25/07 ,  H01L23/00

CPC classification number: H01L25/072 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/48101 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099

公开(公告)号：EP2984680A1

公开(公告)日：2016-02-17

申请号：EP14717118.5

申请日：2014-04-08

Applicant: ABB Technology AG

Inventor： HARTMANN, Samuel ,  DUGAL, Franc ,  EKWALL, Olle ,  DORÉ, Erik

IPC: H01L25/07 ,  H01L23/051

Abstract: The invention relates to a power semiconductor module (10) having a first primary electrode (12), a second primary electrode (14) and a control connection (16). The power semiconductor module (10) further has controllable power semiconductor components (18) which are arranged between the first primary electrode (12) and the second primary electrode (14). According to the invention, the power semiconductor module (10) is characterized in that at least one part of the controllable power semiconductor components (18) are arranged in a ring assembly (28, 28, 28"), wherein the controllable power semiconductor components (18) of the ring assembly (28, 28', 28") are arranged at least approximately along a first circumference (30) of the ring assembly (28, 28', 28") and a control conducting path (32) of the ring assembly (28, 28', 28") is arranged on the first primary electrode (12), wherein the control conducting path (32) extends at least approximately along a second circumference (34) of the ring assembly (28, 28', 28"), and the second circumference (34) extends concentrically to the first circumference (30).

Abstract translation: 本发明涉及具有第一主电极（12），第二主电极（14）和控制连接（16）的功率半导体模块（10）。 功率半导体模块（10）还具有布置在第一主电极（12）和第二主电极（14）之间的可控功率半导体部件（18）。 根据本发明，功率半导体模块（10）的特征在于，可控功率半导体组件（18）的至少一部分布置在环组件（28,28,28“）中，其中可控功率半导体组件 其特征在于，所述环组件（28,28'，28“）的至少大致沿着所述环组件（28,28'，28”）的第一圆周（30）和所述环组件（28,28'，28“）的控制导电路径 所述环形组件（28,28'，28“）布置在所述第一主电极（12）上，其中所述控制导电路径（32）至少大致沿着所述环形组件（28,28）的第二圆周 '，28“），并且第二圆周（34）同心地延伸到第一圆周（30）。

公开(公告)号：EP3046717A1

公开(公告)日：2016-07-27

申请号：EP14720125.5

申请日：2014-04-28

Applicant: ABB Technology AG

Inventor： SIVASUBRAMANIAM, Venkatesh ,  GUILLON, David ,  TRÜSSEL, Dominik ,  THUT, Markus ,  HARTMANN, Samuel

IPC: B23K20/10 ,  B23K20/26

Abstract: The present invention relates to a method of connecting two components by ultrasonic welding for producing a power semiconductor module, said method comprising the steps of: a) Aligning the components to be welded to form a welding interface; b) Aligning a welding tool to the aligned components; c) Removably arranging a trapping material at least partly encompassing the welding interface, whereby the trapping material is a foam; and d) Connecting the components by activating the welding tool. The method like described above provides an easy and cost-saving measure in order to prevent particle contamination when performing a welding process such as particularly an ultrasonic welding process sue to scattered particles.

公开(公告)号：EP2483922A1

公开(公告)日：2012-08-08

申请号：EP10757227.3

申请日：2010-09-28

Applicant: ABB Technology AG

Inventor： SCHULZ, Nicola ,  HARTMANN, Samuel

IPC: H01L25/07 ,  H01L23/00

CPC classification number: H01L24/01 ,  H01L23/4985 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/37599 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48229 ,  H01L2224/4846 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099

Abstract: Exemplary embodiments of the disclosure are directed to a circuit arrangement in which a power functional device and a conductor element are mounted and a method of manufacturing the same. The arrangement includes a substrate, a wiring layer provided on the substrate and electrically connected to the functional device and to the conductor element and an intermediate electric contact device. The intermediate electric contact device is mounted on the wiring layer to provide on the side opposite to the wiring layer a contact region for contacting the conductor element. The conductor element is contacting the intermediate electric contact device in the contact region which is opposite to an area, in which the electric contact device is fixed to the wiring layer.

公开(公告)号：EP2862202A1

公开(公告)日：2015-04-22

申请号：EP13729005.2

申请日：2013-06-06

Applicant: ABB Technology AG

Inventor： HARTMANN, Samuel ,  TRÜSSEL, Dominik

IPC: H01L25/07 ,  H01L23/00

CPC classification number: H01L25/072 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/48101 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099

Abstract: The present invention provides a substrate (1) for mounting multiple power transistors (21, 30) thereon, comprising a first metallization (3), on which the power transistors (21, 30) are commonly mountable with their collector or emitter, and which extends in at least one line (5) on the substrate (1), a second metallization (9), which extends in an area (11) next to the at least one line (5) of the first metallization (3), for connection to the remaining ones of the emitters or collectors of the power transistors (21, 30), and a third metallization (13) for connection to gate contact pads (25) of the power transistors (21, 30), whereby the third metallization (13) comprises a gate contact (15) and at least two gate metallization areas (16, 18), which are interconnectable by way of bonding means (19), the gate metallization areas (16, 18) are arranged in parallel to the at least one line (5) and spaced apart in a longitudinal direction of the at least one line (5), and at least one gate metallization area is provided as a gate island (16) surrounded on the substrate (1) by the second metallization (9). The second metallization (9) is adapted for mounting multiple power transistors (21, 30) with their collectors or emitters thereon, whereby the power transistors (21, 30) have the same orientation like the power transistors (21, 30) mounted on the first metallization (3). The substrate (1 ) comprises a fourth metallization (42), which extends in an area (44) next to the second metallization (9), for connection to the remaining ones of the emitters or collectors of the power transistors (21, 30) mountable on the second metallization (9). A fifth metallization (46) is provided for connection to gate contact pads (25) of the power transistors (21, 30) mountable on the second metallization (9), whereby the fifth metallization (46) comprises at least two gate metallization areas (16, 18), which are interconnectable by way of bonding means (19), the gate metallization areas (16, 18) are arranged in parallel to the at least one line (5) and spaced apart in a longitudinal direction of the at least one line (5), and at least one gate metallization area is provided as a gate island (16) surrounded on the substrate (1 ) by the fourth metallization (42).