METHOD FOR CONTINUOUS WAVEFORM SYNTHESIS
    11.
    发明公开
    METHOD FOR CONTINUOUS WAVEFORM SYNTHESIS 失效
    方法对于连续波形合成

    公开(公告)号:EP0883840A1

    公开(公告)日:1998-12-16

    申请号:EP96937033.0

    申请日:1996-10-29

    CPC classification number: H04L25/03834 G06F1/022

    Abstract: A system for synthesizing a waveform that employs combinatorial logic to generate digital data for each of a set of preselected waveforms. The system includes circuitry for selecting a sequence of the preselected waveform pulses in response to a data signal and circuitry for converting the digital data for the sequence of the preselected waveform pulses into the waveform.

    TRANSISTOR RATIO CONTROLLED CMOS TRANSMISSION LINE EQUALIZER
    12.
    发明公开
    TRANSISTOR RATIO CONTROLLED CMOS TRANSMISSION LINE EQUALIZER 失效
    晶体管比例控制CMOS传输线均衡器

    公开(公告)号:EP0864208A1

    公开(公告)日:1998-09-16

    申请号:EP97924498.0

    申请日:1997-04-11

    Inventor: CHENG, Yi

    CPC classification number: H03H11/0422 H04B3/144

    Abstract: A CMOS transmission line equalizer is provided for receiving distorted signals transmitted through a transmission line and for compensating for the signal distortion. The equalizer has a transfer function characteristic with a single pole and a single zero. The transfer function includes a mirroring ratio circuit (CMR) for controlling the ratio between the single pole and the single zero. The mirroring ratio circuit is controlled by transistor size ratio. The single zero serves to cancel the dominant pole in the transfer function of the transmission line so as to compensate for the signal distortion caused by the transmission line.

    Abstract translation: CMOS传输线均衡器被提供用于接收通过传输线传输的失真信号并且用于补偿信号失真。 均衡器具有单极点和零点的传递函数特性。 传递函数包括用于控制单极点与单个零点之间的比例的镜像比率电路(CMR)。 镜像比例电路由晶体管尺寸比例控制。 单个零点用于消除传输线传递函数中的主导极点,以补偿传输线引起的信号失真。

    CABLE LENGTH ESTIMATION CIRCUIT USING DATA SIGNAL EDGE RATE DETECTION AND ANALOG TO DIGITAL CONVERSION
    15.
    发明公开
    CABLE LENGTH ESTIMATION CIRCUIT USING DATA SIGNAL EDGE RATE DETECTION AND ANALOG TO DIGITAL CONVERSION 失效
    电缆长度估计由边斜率检测数据信号与模拟数字实现

    公开(公告)号:EP0988711A1

    公开(公告)日:2000-03-29

    申请号:EP97952587.0

    申请日:1997-12-18

    CPC classification number: G01B7/02 H03M1/367

    Abstract: A cable length estimation circuit (110) for receiving an input MLT-3 signal provided through an arbitrary length cable (104) and providing a control signal to an equalizer (108) indicating the estimated length of the cable enabling the equalizer (108) to compensate for distortion of the MLT-3 signal resulting from the cable. The cable length estimation circuit (110) includes an edge rate detection circuit (400) for measuring the rate of change in voltage with respect to time during transitions of the MLT-3 signal to provide an indication of cable length. The cable length estimation circuit (110) can also include a digital averaging circuit (402) which provides an average value for signals from the edge rate detection circuit for a desired number of transitions of the MLT-3 signal. The cable length estimation (110) can also include a baseline wander detection circuit (404) which functions so that previous cable length estimations are provided when baseline wander is detected.

    SYSTEM AND METHOD FOR WAVEFORM SYNTHESIS
    16.
    发明公开
    SYSTEM AND METHOD FOR WAVEFORM SYNTHESIS 失效
    系统和方法波形合成

    公开(公告)号:EP0883841A1

    公开(公告)日:1998-12-16

    申请号:EP96937054.0

    申请日:1996-10-29

    CPC classification number: H04L25/03834 G06F1/02 G06F1/022 G06F1/0321

    Abstract: A system for synthesizing a waveform includes waveform synthesis circuitry that generates digital data for each of a set of waveform pulses having preselected slopes at zero-crossing. A sequencer tracks the history of information contained in a data signal and selects a sequence of the waveform pulses in response to the history such that the sequence conveys the history of information while minimizing mismatches between the slopes of adjacent waveform pulses in the sequence.

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