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    PROGRAMMABLE DELAY OF DISRUPT FOR SECURE NETWORKS
    13.
    发明公开
    PROGRAMMABLE DELAY OF DISRUPT FOR SECURE NETWORKS 失效
    可编程报表延迟网络安全

    公开(公告)号：EP0800733A1

    公开(公告)日：1997-10-15

    申请号：EP95939114.0

    申请日：1995-11-08

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： LO, William ,  CRAYFORD, Ian

    IPC: H04L12 ,  H04L29

    CPC classification number: H04L12/44 ,  B60G17/0182 ,  B60G2400/102 ,  B60G2400/202 ,  B60G2600/182 ,  B60G2600/1872 ,  B60G2600/1873 ,  B60G2800/162 ,  H04L12/22 ,  H04L63/0236

    Abstract: A secure repeater (20) implementing data packet masking includes a programmable and selective, on a per port basis, delay disrupt response. A delay disrupt controller (70) receives signals indicating retransmissions of fields from a data packet. These signals include a destination address field and a source address field. A plurality of memories, one associated with each port, determines the associated port's delay response to the data packet. Each memory stores a delay disrupt control code. When the delay disrupt control code for a particular port has a value indicating that the associated port is enabled to delay disruption of a data packet, security marking is disabled until the source address field is retransmitted from the particular port.

    MULTIPLE ADDRESS SECURITY ARCHITECTURE
    15.
    发明公开
    MULTIPLE ADDRESS SECURITY ARCHITECTURE 失效
    多ADDRESSABLE安全体系

    公开(公告)号：EP0830762A1

    公开(公告)日：1998-03-25

    申请号：EP96911584.0

    申请日：1996-04-04

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： LO, William ,  CRAYFORD, Ian

    IPC: H04L9 ,  H04L12 ,  H04L29

    CPC classification number: H04L63/02 ,  H04L12/22 ,  H04L12/44 ,  H04L12/4625

    Abstract: A secure repeater (20) implementing data packet masking includes a programmable and selective, on a per port basis, disrupt response responsive to any of several selectable qualifying conditions. A disrupt controller (70) receives signals indicating various characteristics of fields of a data packet, and other conditions. A register bank (76) includes a plurality of memories, one associated with each port and some of the conditions, assists the disrupt controller to determine the associated port's disrupt response to the data packet. Each memory stores a disrupt control code. When the disrupt control code for a particular port has a value indicating that the associated port is enabled, deassertion of a condition signal associated with that control code results in disruption of a data packet. A cell array (200) permits simple, efficient scaling and formation of integrated semiconductor structures to implement complex disrupt logic equations.

    OPTIMIZED MII FOR 802.3U (100 BASE-T) FAST ETHERNET PHYS
    16.
    发明公开
    OPTIMIZED MII FOR 802.3U (100 BASE-T) FAST ETHERNET PHYS 失效
    增强了对MII 802.3U（100 BASE-T）快速以太网PHYS

    公开(公告)号：EP0925669A1

    公开(公告)日：1999-06-30

    申请号：EP97908919.0

    申请日：1997-03-06

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： CRAYFORD, Ian ,  SIVAKOLUNDU, Ramesh ,  CHENG, Bing

    IPC: H04L12

    CPC classification number: H04L12/44

    Abstract: A media independent interface for interconnecting an integrated repeater front-end with one or more integrated interface devices, each having several physical layer devices for operation in conformance with IEEE 802.3u. The media independent interface, in a repeater implementation, shares transmit and receive data channels, and provides for dedicated control signals, thereby multiplexing shared channels across all of the physical layer devices in the integrated interface device.

    FLOW CONTROL METHOD AND APPARATUS FOR ETHERNET PACKET SWITCHED HUB
    17.
    发明公开
    FLOW CONTROL METHOD AND APPARATUS FOR ETHERNET PACKET SWITCHED HUB 失效
    方法和系统的河段为以太网分组交换节点控制

    公开(公告)号：EP0830769A1

    公开(公告)日：1998-03-25

    申请号：EP96911582.0

    申请日：1996-04-04

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： CRAYFORD, Ian

    IPC: H04L12

    CPC classification number: H04L47/10 ,  H04L12/46 ,  H04L47/135 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/40 ,  H04L49/506

    Abstract: A flow control enabled Ethernet switch that applies backpressure to input ports that attempt to transmit a data packet to a busy destination port. The backpressure is a phantom packet that activates the IEEE 802.3 collision detection system to abort transmission of the data packet. A subsequent series of phantom packets (that are invalid) provide carrier activity that inhibits retransmission of the packet. When the destination port is available, the phantom packets are stopped, permitting standard retransmission of the data packet. The switch includes prioritization mechanisms (e.g., a throttle count) to use when awarding priority to a port having backpressure applied.

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