公开(公告)号：JP2011142631A

公开(公告)日：2011-07-21

申请号：JP2011000645

申请日：2011-01-05

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/033 ,  H04L7/04 ,  G11C7/22 ,  H03K5/00 ,  H03K19/173 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/02

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/0337

Abstract: PROBLEM TO BE SOLVED: To provide a clock data recovery circuitry provided on or associated with a programmable logic device circuitry.
SOLUTION: A programmable logic device ("PLD") is augmented with programmable clock data recovery ("CDR") circuitry to allow the PLD to communicate via any one of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ("LVDS"). The circuitry may be part of a larger system.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供在可编程逻辑器件电路上或与可编程逻辑器件电路相关联的时钟数据恢复电路。 解决方案：可编程逻辑器件（“PLD”）用可编程时钟数据恢复（“CDR”）电路进行扩充，以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以与PLD集成，或者其可以全部或部分地在单独的集成电路上。 电路可能能够进行CDR输入，CDR输出或两者。 CDR能力可以与其他非CDR信令能力组合提供，例如非CDR低电压差分信号（“LVDS”）。 电路可以是较大系统的一部分。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010172014A

公开(公告)日：2010-08-05

申请号：JP2010101545

申请日：2010-04-26

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： AUNG EDWARD ,  LUI HENRY ,  BUTLER PAUL ,  TURNER JOHN ,  PATEL RAKESH ,  LEE CHONG

IPC: H04L7/033 ,  H04L7/04 ,  G11C7/22 ,  H03K19/177 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/02

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/0337

Abstract: PROBLEM TO BE SOLVED: To provide clock data recovery circuitry provided on or associated with programmable logic device circuitry. SOLUTION: A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ("LVDS"). The circuitry may be part of a larger system. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供在可编程逻辑器件电路上提供或与可编程逻辑器件电路相关联的时钟数据恢复电路。 解决方案：可编程逻辑器件（“PLD”）用可编程时钟数据恢复（“CDR”）电路进行扩充，以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以与PLD集成，或者其可以全部或部分地在单独的集成电路上。 电路可能能够进行CDR输入，CDR输出或两者。 CDR能力可以与其他非CDR信令能力组合提供，例如非CDR低电压差分信号（“LVDS”）。 电路可以是较大系统的一部分。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007209032A

公开(公告)日：2007-08-16

申请号：JP2007117754

申请日：2007-04-26

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： STARR GREG ,  AUNG EDWARD

IPC: G06F1/04 ,  H03K5/26 ,  G06F1/08 ,  G06F1/12 ,  H03K5/00 ,  H03K5/19 ,  H03K17/00 ,  H03L7/00 ,  H03L7/095 ,  H03L7/14 ,  H04L7/00

CPC classification number: G06F11/1604 ,  G06F1/08 ,  G06F11/20 ,  H03L7/095 ,  H03L7/143 ,  H04L7/0008 ,  H04L7/0083

Abstract: PROBLEM TO BE SOLVED: To provide an appropriate circuit which detects clock loss and carries out switch over of clock signals. SOLUTION: There are included a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. There are further included a clock loss sense circuit and method that utilizes counters and reset signals to compare primary clock and secondary clock signals. The clock loss sense circuit is included which uses counters and edge sensors to speedily and easily determine loss of the primary clock signal. The cross switchover circuit is included to be responsive to both the clock loss signal and the additional switch command signal. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种检测时钟损耗并执行时钟信号切换的适当电路。 解决方案：包括时钟丢失检测和切换电路和方法，其中时钟切换响应于主信号的丢失和附加的开关命令信号。 还包括利用计数器和复位信号比较主时钟和次时钟信号的时钟损耗检测电路和方法。 包括时钟损耗检测电路，其使用计数器和边缘传感器来快速且容易地确定主时钟信号的损耗。 交叉切换电路包括响应于时钟损耗信号和附加开关命令信号。 版权所有（C）2007，JPO＆INPIT