公开(公告)号：JP2011193505A

公开(公告)日：2011-09-29

申请号：JP2011100172

申请日：2011-04-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04L25/03 ,  H04B3/06

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptation circuit network and a method for a programmable logic device.
SOLUTION: The method controls the equalization of an incoming data signal. The method includes steps for: detecting bits having two consecutive different values out of the data signal; determining whether transition in the incoming data signal between the two bits is relatively low in speed or relatively high in speed; and increasing the equalization of the incoming data signal when the transition is relatively low in speed.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供数字适配电路网络和可编程逻辑器件的方法。

解决方案：该方法控制输入数据信号的均衡。 该方法包括以下步骤：从数据信号中检测具有两个连续不同值的位; 确定两个比特之间的输入数据信号中的转换是相对低的速度还是相对较高的速度; 并且当转换速度相对较低时，增加输入数据信号的均衡。 版权所有（C）2011，JPO＆INPIT