公开(公告)号：US20160098144A1

公开(公告)日：2016-04-07

申请号：US14923246

申请日：2015-10-26

Applicant: Apple Inc.

Inventor： Byung Duk Yang ,  Szu-Hsien Lee ,  Kyung Wook Kim ,  Shih Chang Chang ,  Chun-Yao Huang ,  Hao-Lin Chiu

IPC: G06F3/041 ,  G09G3/36 ,  G06F3/044

CPC classification number: G09G3/3648 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13456 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04104 ,  G06F2203/04112 ,  G09F9/30 ,  G09G3/3666 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0281 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

Abstract translation: 显示器可以具有排列成行和列的像素阵列。 每个像素可以具有用于控制与该像素相关联的输出光量的晶体管。 晶体管可以是具有有源区的薄膜晶体管，第一和第二源极 - 漏极端子和栅极。 栅极线可用于将栅极控制信号分配到每行中的晶体管的栅极。 垂直于栅极线延伸的数据线可用于沿像素列分布图像数据。 栅极线可以连接到平行于数据线延伸的栅极线扩展。 数据线可以各自重叠相应的一个栅极线延伸。 通孔可用于将栅极线延伸部分连接到栅极线。 门线扩展可能都具有相同的长度。

公开(公告)号：US20160042707A1

公开(公告)日：2016-02-11

申请号：US14472272

申请日：2014-08-28

Applicant: Apple Inc.

Inventor： Chaohao WANG ,  Szu-Hsien Lee ,  Paolo SACCHETTO ,  Shih Chang Chang ,  Chun-Yao Huang ,  Paul S. DRZAIC

IPC: G09G3/36 ,  G09G3/34

CPC classification number: G09G3/3266 ,  G09G3/2044 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2310/04 ,  G09G2320/0247 ,  G09G2320/0673 ,  G09G2330/021 ,  G09G2340/0435

Abstract: This application relates to methods and apparatus for refreshing a display device at various frequencies. Specifically, multiple areas of the display device can be refreshed concurrently at different frequencies. In this way, when static content is being displayed in certain areas of the display device, those certain areas can be refreshed at a lower rate than areas displaying dynamic content such as video or animation. By refreshing at lower rates, the energy consumed by the display device and subsystems associated with the display device can be reduced. Additionally, processes for reducing flicker when refreshing the display device at different refresh rates are disclosed herein.

公开(公告)号：US20150346528A1

公开(公告)日：2015-12-03

申请号：US14494498

申请日：2014-09-23

Applicant: Apple Inc.

Inventor： Zhibing Ge ,  Enkhamgalan Dorjgotov ,  Cheng Chen ,  Lei Zhao ,  Chun-Yao Huang ,  Shih-Chang Chang ,  Shih-Chyuan Fan Jiang

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1362

CPC classification number: G02F1/13624 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136213 ,  G02F1/136277 ,  G02F1/1368

Abstract: A liquid crystal display may have a layer of liquid crystal material. The display may have an array of display pixel circuits. The display pixel circuits may each include a display pixel electrode that applies electric fields to a corresponding portion of the liquid crystal material. Thin-film transistor circuitry and other structures in the display pixels may control operation of the display pixels circuits. The thin-film transistor circuitry may be configured to handle operation of the display at multiple refresh rates. To accommodate multiple refresh rates, each pixel circuit may include a pair of transistors. A first transistor is used to apply data signals from a data line to the display pixel electrode. A storage capacitor is used to maintain the data signal on the electrode. The second transistor may be used to adjust the capacitance of the storage capacitor depending on the refresh rate of the display.

Abstract translation: 液晶显示器可以具有液晶材料层。 显示器可以具有显示像素电路的阵列。 显示像素电路可以各自包括将电场施加到液晶材料的对应部分的显示像素电极。 显示像素中的薄膜晶体管电路和其他结构可以控制显示像素电路的操作。 薄膜晶体管电路可以被配置为以多个刷新速率处理显示器的操作。 为了适应多个刷新率，每个像素电路可以包括一对晶体管。 第一晶体管用于将数据信号从数据线施加到显示像素电极。 使用存储电容器来维持电极上的数据信号。 第二晶体管可以用于根据显示器的刷新率来调整存储电容器的电容。

公开(公告)号：US20150339563A1

公开(公告)日：2015-11-26

申请号：US14699417

申请日：2015-04-29

Applicant: Apple Inc.

Inventor： Kwang Soon Park ,  Ming-Chin Hung ,  Chun-Yao Huang ,  Shih Chang Chang ,  Ming-Yuh Hsu

IPC: G06K19/077 ,  G02F1/1335 ,  G06K7/10 ,  G02F1/133

CPC classification number: G06K19/0772 ,  G02F1/13306 ,  G02F1/133512 ,  G02F1/133528 ,  G02F1/1368 ,  G02F2001/133388 ,  G06K7/10198

Abstract: A display may have an active area surrounded by an inactive border area. The display may be a liquid crystal display having a liquid crystal layer sandwiched between a color filter layer and a thin-film transistor layer. An upper polarizer may have a polarized central region that overlaps the active area of the display. The upper polarizer may also have an unpolarized portion in the inactive border area overlapping the border structures. The border structures may include colored material such as a white layer on the inner surface of the thin-film transistor layer. Binary information may be embedded into an array of programmable resonant circuits. The binary information may be a display identifier or other information associated with a display. The programmable resonant circuits may be tank circuits with adjustable capacitors, fuses, or other programmable components.

Abstract translation: 显示器可以具有被非活动边界区域包围的活动区域。 显示器可以是具有夹在滤色器层和薄膜晶体管层之间的液晶层的液晶显示器。 上偏振器可以具有与显示器的有效区域重叠的偏振中心区域。 上偏振器还可以在非边界区域中具有与边界结构重叠的非偏振部分。 边界结构可以在薄膜晶体管层的内表面上包括诸如白色层的着色材料。 二进制信息可嵌入到可编程谐振电路阵列中。 二进制信息可以是与显示器相关联的显示标识符或其他信息。 可编程谐振电路可以是具有可调电容器，保险丝或其他可编程元件的储能电路。

公开(公告)号：US20150220194A1

公开(公告)日：2015-08-06

申请号：US14489338

申请日：2014-09-17

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: G06F3/041

CPC classification number: G06F3/0412 ,  G06F3/0416

Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing, (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

Abstract translation: 触摸屏显示器可以包括耦合到显示像素阵列的栅极线驱动器电路。 显示器可以具有帧内暂停（IFP）能力，其中可以在一个或多个帧内消隐间隔期间执行触摸或其它操作。 在一种合适的布置中，栅极驱动电路可以包括多个栅极线驱动器段，每个栅驱动器段由单独的栅极起始脉冲激活。 每个栅极起始脉冲只能在IFP间隔结束时释放。 在另一种合适的布置中，虚拟栅极驱动器单元可插入有源栅极驱动器单元中。 栅极输出信号可能在IFP内部传播通过虚拟栅极驱动器单元。 在另一种合适的布置中，每个有源栅极驱动器单元可以设置有缓冲部分，其保护栅极驱动器单元中的至少一些晶体管免受不期望的应力。

公开(公告)号：US08987049B2

公开(公告)日：2015-03-24

申请号：US14474433

申请日：2014-09-02

Applicant: Apple Inc.

Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract translation: 提供了制造薄膜晶体管（TFT）的方法。 该方法包括在覆盖栅电极的栅极绝缘体上形成半导体层，以及在半导体层上沉积绝缘体层，以及蚀刻绝缘体层以形成图案化蚀刻停止件，而不会失去栅极绝缘体。 该方法还包括在半导体层和图案化蚀刻停止物上形成源电极和漏电极。 该方法还包括：除了源电极和漏电极之外的半导体层的一部分，使得半导体层的剩余部分在源电极和栅电极的第一重叠区域和第二重叠区域中覆盖栅极绝缘体 的漏电极和栅电极。

公开(公告)号：US20140141565A1

公开(公告)日：2014-05-22

申请号：US13679767

申请日：2012-11-16

Applicant: APPLE INC.

Inventor： Ming-Chin Hung ,  Young Bae Park ,  Chun-Yao Huang ,  Shih Chang Chang ,  John Z. Zhong

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869

Abstract: Embodiments of the present disclosure relate to display devices and methods for manufacturing display devices. Specifically, embodiments of the present disclosure employ an enhanced etching process to create uniformity in the gate insulator of thin-film-transistor (TFTs) by using an active layer to protect the gate insulator from inadvertent etching while patterning an etch stop layer.

Abstract translation: 本公开的实施例涉及用于制造显示设备的显示设备和方法。 具体地，本公开的实施例采用增强的蚀刻工艺，以通过使用有源层来在薄膜晶体管（TFT）的栅极绝缘体中产生均匀性，以保护栅极绝缘体免受无意蚀刻，同时图案化蚀刻停止层。

公开(公告)号：US20140042427A1

公开(公告)日：2014-02-13

申请号：US13629537

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract translation: 提供了制造薄膜晶体管（TFT）的方法。 该方法包括在覆盖栅电极的栅极绝缘体上形成半导体层，以及在半导体层上沉积绝缘体层，以及蚀刻绝缘体层以形成图案化蚀刻停止件，而不会失去栅极绝缘体。 该方法还包括在半导体层和图案化蚀刻停止物上形成源电极和漏电极。 该方法还包括：除了源电极和漏电极之外的半导体层的一部分，使得半导体层的剩余部分在源电极和栅电极的第一重叠区域和第二重叠区域中覆盖栅极绝缘体 的漏电极和栅电极。

公开(公告)号：US20130235003A1

公开(公告)日：2013-09-12

申请号：US13661839

申请日：2012-10-26

Applicant: APPLE INC.

Inventor： Shih Chang Chang ,  Young Bae Park ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Szu-Hsien Lee

IPC: G06F3/038

CPC classification number: G09G3/3677

Abstract: Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed.

Abstract translation: 栅极线驱动器电路将输出脉冲施加到用于显示元件阵列的多个栅极线中的每一个。 电路具有多个栅极驱动器，每个栅极驱动器被耦合以驱动相应的一条栅极线。 每个栅极驱动器具有输出级，其中高侧晶体管和低侧晶体管耦合以响应于至少一个时钟信号驱动相应的栅极线。 耦合下拉晶体管以放电输出级的控制电极。 具有共源共栅放大器的控制电路被耦合以作为a）至少一个时钟信号和b）来自控制电极的反馈来驱动下拉晶体管。 还描述和要求保护其他实施例。

公开(公告)号：US20250111830A1

公开(公告)日：2025-04-03

申请号：US18978711

申请日：2024-12-12

Applicant: Apple Inc.

Inventor： Bilin Wang ,  Tien-Chien Kuo ,  Kanghoon Jeon ,  Chun-Yao Huang

IPC: G09G3/3291 ,  G09G3/36 ,  G09G5/397

Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.