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公开(公告)号：EP1060287A1
公开(公告)日：2000-12-20
申请号：EP99911165.1
申请日：1999-03-05
Applicant: ASM America, Inc.
Inventor： RAAIJMAKERS, Ivo , POMAREDE, Christophe, François, Lilian , VAN DER JEUGD, Cornelius, Alexander , GSCHWANDTNER, Alexander , GRASSL, Andreas
CPC classification number: C23C16/45504 , C23C16/045 , C23C16/24 , C23C16/455 , C23C16/45502 , C23C16/45591 , H01L21/02381 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/28525 , H01L21/28556 , H01L21/76877 , H01L29/66181 , H01L29/78
Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650 °C. Silane and hydrogen are flowed over a substrate (100) in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater than 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon (101) into extremely deep trenches (100) and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.
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公开(公告)号：EP1036406A2
公开(公告)日：2000-09-20
申请号：EP98956476.0
申请日：1998-11-02
Applicant: ASM America, Inc.
Inventor： GOODMAN, Matthew, G. , RAAIJMAKERS, Ivo , JACOBS, Loren, R. , VAN BILSEN, Franciscus, B., M. , MEYER, Michael, J. , BARRETT, Eric, Alan
IPC: H01L21/00
CPC classification number: H01L21/68735 , C23C16/4581 , C23C16/4585 , C23C16/481 , H01L21/68721 , H01L21/68728 , H01L21/68785
Abstract: Improvements in the design of a low mass wafer holder are disclosed. The improvements include the use of peripherally located, integral lips to space a wafer or other substrate above the base plate of the wafer holder. A uniform gap is thus provided between the wafer and the base plate, such as will temper rapid heat exchanges, allow gas to flow between the wafer and wafer holder during wafer pick-up, and keep the wafer holder thermally coupled with the wafer. At the same time, thermal disturbance from lip contact with the wafer is reduced. Gas flow during pick-up can be provided through radial channels in a wafer holder upper surface, or through backside gas passages. A thicker ring is provided at the wafer holder perimeter, and is provided in some embodiments as an independent piece to accommodate stresses accompanying thermal gradients. A self-centering mechanism is provided to keep the wafer holder centered relative to a spider which is subject to differential thermal expansion.
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公开(公告)号：EP1029109A1
公开(公告)日：2000-08-23
申请号：EP98957469.4
申请日：1998-11-02
Applicant: ASM America, Inc.
Inventor： WENGERT, John, F. , RAAIJMAKERS, Ivo , HALPIN, Mike , JACOBS, Loren , MEYER, Michael, J. , VAN BILSEN, Frank , GOODMAN, Matt , BARRETT, Eric , WOOD, Eric , SAMUELS, Blake
CPC classification number: H01L21/67115 , C23C16/4401 , C23C16/481 , G01K1/12 , G01K7/04
Abstract: A generally horizontally-oriented quartz CVD chamber (10) is disclosed with front and rear chamber divider plates (16, 18) adjacent a centrally positioned susceptor (20) and surrounding temperature control ring (22) which divide the chamber into upper and lower regions. Improvement to the lifetime of CVD process components and related throughput improvements are disclosed. A getter plate (30) for attracting some of the unused reactant gas is positioned downstream from the susceptor extending generally parallel to and spaced between the divider plate and the upper chamber wall. This getter plate also minimizes deposition on the chamber walls and improves the efficiency of a cleaning step. Reradiating elements are also located adjacent side walls of the chamber to heat cooler chamber wall areas. The getter plate and the reradiating elements plus the susceptor and surrounding ring are all made of solid chemical vapor deposited SiC to improve the life of the chamber. Also, thermocouples (34) adjacent the susceptor are provided with SiC sheaths to enable the thermocouples to withstand more process cycles than that of quartz sheaths. SiC shields may be provided on quartz components throughout the chamber to protect the quartz from devitrification. Throughput is improved by both reducing down time and reducing the cleaning step time of the process cycle.
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公开(公告)号：EP1029109B1
公开(公告)日：2007-09-26
申请号：EP98957469.4
申请日：1998-11-02
Applicant: ASM America, Inc.
Inventor： WENGERT, John, F. , RAAIJMAKERS, Ivo , HALPIN, Mike , JACOBS, Loren , MEYER, Michael, J. , VAN BILSEN, Frank , GOODMAN, Matt , BARRETT, Eric , WOOD, Eric , SAMUELS, Blake
CPC classification number: H01L21/67115 , C23C16/4401 , C23C16/481 , G01K1/12 , G01K7/04
Abstract: A generally horizontally-oriented quartz CVD chamber (10) is disclosed with front and rear chamber divider plates (16, 18) adjacent a centrally positioned susceptor (20) and surrounding temperature control ring (22) which divide the chamber into upper and lower regions. Improvement to the lifetime of CVD process components and related throughput improvements are disclosed. A getter plate (30) for attracting some of the unused reactant gas is positioned downstream from the susceptor extending generally parallel to and spaced between the divider plate and the upper chamber wall. This getter plate also minimizes deposition on the chamber walls and improves the efficiency of a cleaning step. Reradiating elements are also located adjacent side walls of the chamber to heat cooler chamber wall areas. The getter plate and the reradiating elements plus the susceptor and surrounding ring are all made of solid chemical vapor deposited SiC to improve the life of the chamber. Also, thermocouples (34) adjacent the susceptor are provided with SiC sheaths to enable the thermocouples to withstand more process cycles than that of quartz sheaths. SiC shields may be provided on quartz components throughout the chamber to protect the quartz from devitrification. Throughput is improved by both reducing down time and reducing the cleaning step time of the process cycle.
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公开(公告)号：EP1060287B1
公开(公告)日：2005-01-26
申请号：EP99911165.1
申请日：1999-03-05
Applicant: ASM America, Inc.
Inventor： RAAIJMAKERS, Ivo , POMAREDE, Christophe, François, Lilian , VAN DER JEUGD, Cornelius, Alexander , GSCHWANDTNER, Alexander , GRASSL, Andreas
CPC classification number: C23C16/45504 , C23C16/045 , C23C16/24 , C23C16/455 , C23C16/45502 , C23C16/45591 , H01L21/02381 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/28525 , H01L21/28556 , H01L21/76877 , H01L29/66181 , H01L29/78
Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650 °C. Silane and hydrogen are flowed over a substrate (100) in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater than 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon (101) into extremely deep trenches (100) and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.
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Patent Agency Ranking
公开(公告)号：EP1221177A1
公开(公告)日：2002-07-10
申请号：EP00957751.1
申请日：2000-08-24
Applicant: ASM America, Inc.
Inventor： RAAIJMAKERS, Ivo , HAUKKA, Suvi, P. , GRANNEMAN, Ernst, H., A. , SAANILA, Ville, Antero , SOININEN, Pekka, Juha , ELERS, Kai-Erik
IPC: H01L21/768 , H01L23/532 , C23C16/00
CPC classification number: C23C16/45525 , C23C16/0272 , C23C16/045 , C23C16/08 , C23C16/32 , C23C16/44 , C30B25/02 , C30B29/02 , C30B29/36 , H01L21/28562 , H01L21/7681 , H01L21/76843 , H01L21/76873 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53242 , H01L23/53252 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches (60) and contact vias (62) are formed (100) in insulating layers (60, 56). The trenches (60) and vias (62) are exposed to alternating chemistries to form monolayers of a desired lining material (150). Exemplary process flows include alternately pulsed metal halide (104) and ammonia gases (108) injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal (160) for any given trench and via dimensions.
Abstract translation: 提供了用于集成电路中的双镶嵌结构的共形衬里的方法和结构。 在绝缘层（60,56）中形成沟槽（60）和接触孔（62）（100）。 沟槽（60）和通孔（62）暴露于交替的化学物质以形成期望的内衬材料（150）的单层。 示例性的工艺流程包括交替地将脉冲金属卤化物（104）和氨气（108）注入恒定的载体流中。 自终止的金属层因此与氮反应。 对于任何给定的沟槽和通孔尺寸，近乎完美的台阶覆盖允许扩散屏障功能的最小厚度，从而最大化随后的填充金属（160）的体积。
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公开(公告)号：EP1044291A1
公开(公告)日：2000-10-18
申请号：EP99901394.9
申请日：1999-01-08
Applicant: ASM America, Inc.
Inventor： FERRO, Armand , RAAIJMAKERS, Ivo , FOSTER, Derrick
CPC classification number: C30B29/06 , C23C16/4405 , C23C16/481 , C30B25/02 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/02301 , H01L21/02332 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/28017 , H01L21/31116 , H01L21/31612 , H01L21/31662 , H01L29/66651
Abstract: A single-wafer, chemical vapor deposition reactor (10) is provided with hydrogen and silicon source gases (72, 74, 86) suitable for epitaxial silicon deposition, as well as a safe mixture (70) of oxygen in a non-reactive gas. Methods are provided for forming oxide and silicon layers within the same chamber (12). In particular, a sacrificial oxidation (102) is performed, followed by a hydrogen bake (104) to sublime the oxide and leave a clean substrate. Epitaxial deposition (106) can follow in situ. A protective oxide can also be formed (108) over the epitaxial layer within the same chamber, preventing contamination of the critical epitaxial layer. Alternatively, the oxide layer (124) can serve as the gate dielectric, and a polysilicon gate layer (126) can be formed (112) in situ over the oxide (124).
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公开(公告)号：EP1116261B1
公开(公告)日：2006-11-15
申请号：EP99948071.8
申请日：1999-08-26
Applicant: ASM America, Inc.
Inventor： RAAIJMAKERS, Ivo
CPC classification number: H01L21/67109 , C23C16/54 , C23C16/56 , C30B25/10
Abstract: Methods and apparatuses are provided for cooling semiconductor substrates prior to handling. In one embodiment, a substrate and support structure combination is lifted after high temperature processing to a cold wall of a thermal processing chamber, which acts as a heat sink. Conductive heat transfer across a small gap from the substrate to the heat sink speeds wafer cooling prior to handling the wafer (e.g., with a robot). In another embodiment, a separate plate is kept cool within a pocket during processing, and is moved close to the substrate and support after processing. In yet another embodiment, a cooling station between a processing chamber and a storage cassette includes two movable cold plates, which are movable to positions closely spaced on either side of the wafer.
Abstract translation: 在处理之前提供了用于冷却半导体衬底的方法和装置。 在一个实施例中，将衬底和支撑结构组合在高温处理之后提升到用作散热器的热处理室的冷壁。 从衬底到散热器的小间隙的导电热传递在处理晶片之前（例如，使用机器人）加速晶片冷却。 在另一个实施例中，单独的板在加工期间保持在凹槽内冷却，并且在处理之后移动靠近基板并支撑。 在另一个实施例中，处理室和存储盒之间的冷却站包括两个可移动的冷板，其可移动到在晶片的任一侧上紧密间隔开的位置。
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19.发明公开
公开(公告)号：EP1098830A2
公开(公告)日：2001-05-16
申请号：EP99933854.4
申请日：1999-07-08
Applicant: ASM America, Inc.
Inventor： CARR, Paul, R. , JACOBSON, Paul, T. , KUSBEL, James, F. , ROUNDY, James, S. , AGGARWAL, Ravinder, K. , RAAIJMAKERS, Ivo , LENZ, Rod , RAJBHARTI, Nilesh
CPC classification number: H01L21/68735 , H01L21/67346 , H01L21/67778 , H01L21/68721 , H01L21/68728 , H01L21/68764 , H01L21/68771 , Y10S414/137 , Y10S414/141
Abstract: Disclosed is a carrier (10) comprising three support elements (50) connected by an underlying frame (15). The periphery of a wafer (45) rests upon the support elements (50). Also disclosed is a wafer handler (25) with a plurality of arms (100). Spacers (85) space the carrier (10) above a base plate (90) associated with a station in a wafer handling area. An arm (100) slides beneath the frame (15) and between the spacers (85), but the handler (25) does not contact the wafer (45). A method of using the handler (25) and carrier (10) is provided where the handler (55) lifts and rotates the carrier (10) with the wafer (45) through various stations (112, 125, 126 and 130) in a wafer handling area (95). A control device (33) reduces the handler speed only at critical points of the processing cycle. The handler (55) is capable of moving a plurality of carriers (10) and wafers (45) simultaneously.
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公开(公告)号：EP1038314A1
公开(公告)日：2000-09-27
申请号：EP98960377.4
申请日：1998-11-20
Applicant: ASM America, Inc.
Inventor： RAAIJMAKERS, Ivo , JACOBS, Loren, R. , HALPIN, Michael, W. , ALEXANDER, James, A. , O'NEILL, Ken , GOODWIN, Dennis, L.
CPC classification number: H01L21/68785 , H01L21/68707 , Y10S294/902 , Y10S414/141
Abstract: A system for facilitating wafer transfer comprises a susceptor unit (150) consisting of an inner susceptor section (152) which rests within an outer susceptor section (154). A vertically movable and rotatable support spider (120) located beneath the susceptor unit can rotate into positions to engage either the inner or the outer susceptor sections. When the inner section is engaged, for loading/unloading, the support spider lifts the inner section vertically out of the outer section. When the outer section is engaged, for processing, the support spider raises and lowers the entire unit. A robotic arm end effector (200) engages only the lower surface of the outer edge of the wafer (210), which overhangs from the inner section when supported by the inner section alone, thereby enabling transfer of the wafer back and forth between the robotic arm and the susceptor. Various species of end effectors are disclosed.
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