SYSTEM FOR PARALLEL INTRA-PREDICTION DECODING OF VIDEO DATA
    11.
    发明申请
    SYSTEM FOR PARALLEL INTRA-PREDICTION DECODING OF VIDEO DATA 有权
    并行预测系统解码视频数据

    公开(公告)号:US20130114711A1

    公开(公告)日:2013-05-09

    申请号:US13729914

    申请日:2012-12-28

    Abstract: A system for decoding video data includes a processing unit. The processing unit includes a plurality of processing pipelines and a driver. The driver includes a decoder configured to generate a plurality of intermediate control maps containing control information including an indication of which macro blocks or portions of macro blocks may be processed in parallel in the plurality of processing pipelines.

    Abstract translation: 视频数据解码系统包括处理单元。 处理单元包括多个处理管线和驱动器。 驱动器包括:解码器,被配置为生成包含控制信息的多个中间控制图,所述控制信息包括可以在多个处理流水线中并行处理哪些宏块或宏块的一部分的指示。

    Low power and low latency GPU coprocessor for persistent computing

    公开(公告)号:US11625807B2

    公开(公告)日:2023-04-11

    申请号:US17181300

    申请日:2021-02-22

    Abstract: Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.

    Software only intra-compute unit redundant multithreading for GPUs
    13.
    发明授权
    Software only intra-compute unit redundant multithreading for GPUs 有权
    用于GPU的软件内部计算单元冗余多线程

    公开(公告)号:US09367372B2

    公开(公告)日:2016-06-14

    申请号:US13920574

    申请日:2013-06-18

    Abstract: A system, method and computer program product to execute a first and a second work-item, and compare the signature variable of the first work-item to the signature variable of the second work-item. The first and the second work-items are mapped to an identifier via software. This mapping ensures that the first and second work-items execute exactly the same data for exactly the same code without changes to the underlying hardware. By executing the first and second work-items independently, the underlying computation of the first and second work-item can be verified. Moreover, system performance is not substantially affected because the execution results of the first and second work-items are compared only at specified comparison points.

    Abstract translation: 一种用于执行第一和第二工作项目的系统,方法和计算机程序产品,并且将第一工作项目的签名变量与第二工作项目的签名变量进行比较。 第一个和第二个工作项通过软件映射到一个标识符。 此映射确保第一个和第二个工作项完全相同的数据完全相同的代码,而不会更改底层硬件。 通过独立地执行第一和第二工作项目,可以验证第一和第二工件的基础计算。 此外,系统性能基本上不受影响,因为第一和第二工作项目的执行结果仅在指定的比较点进行比较。

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