公开(公告)号：US11614791B2

公开(公告)日：2023-03-28

申请号：US17111294

申请日：2020-12-03

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Peter F. Holland ,  Rohit K. Gupta ,  Brad W. Simeral

IPC: G06F1/3234 ,  G09G3/20 ,  G06F1/18 ,  G06F1/3218

Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

公开(公告)号：US20220083122A1

公开(公告)日：2022-03-17

申请号：US17111294

申请日：2020-12-03

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Peter F. Holland ,  Rohit K. Gupta ,  Brad W. Simeral

IPC: G06F1/3234 ,  G09G3/20 ,  G06F1/18 ,  G06F1/3218

Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

公开(公告)号：US20210034527A1

公开(公告)日：2021-02-04

申请号：US16530216

申请日：2019-08-02

Applicant: Apple Inc.

Inventor： Wolfgang H. Klingauf ,  Connie W. Cheung ,  Rohit K. Gupta ,  Rohit Natarajan ,  Vanessa Cristina Heppolette ,  Varaprasad V. Lingutla ,  Muditha Kanchana

IPC: G06F12/0842 ,  G06F12/0895

Abstract: Systems, apparatuses, and methods for dynamically partitioning a memory cache among a plurality of agents are described. A system includes a plurality of agents, a communication fabric, a memory cache, and a lower-level memory. The partitioning of the memory cache for the active data streams of the agents is dynamically adjusted to reduce memory bandwidth and increase power savings across a wide range of applications. A memory cache driver monitors activations and characteristics of the data streams of the system. When a change is detected, the memory cache driver dynamically updates the memory cache allocation policy and quotas for the agents. The quotas specify how much of the memory cache each agent is allowed to use. The updates are communicated to the memory cache controller to enforce the new policy and enforce the new quotas for the various agents accessing the memory.

公开(公告)号：US20250068229A1

公开(公告)日：2025-02-27

申请号：US18908018

申请日：2024-10-07

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/3287 ,  G06F1/3228 ,  H04B17/318

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US20240126457A1

公开(公告)日：2024-04-18

申请号：US18535697

申请日：2023-12-11

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F3/06 ,  G06F12/0831

CPC classification number: G06F3/0631 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0835 ,  G06F2212/1021

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：US20240094797A1

公开(公告)日：2024-03-21

申请号：US18476547

申请日：2023-09-28

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/3287 ,  G06F1/3228

CPC classification number: G06F1/3287 ,  G06F1/3228 ,  H04B17/318

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US20230394276A1

公开(公告)日：2023-12-07

申请号：US17833476

申请日：2022-06-06

Applicant: Apple Inc.

Inventor： Sayyed Karen Khatamifard ,  Chenfan Sun ,  Alon Yaakov ,  Husam Khashiboun ,  Jeffrey D. Marker ,  Saman Naderiparizi ,  Ramana V. Rachakonda ,  Rohit K. Gupta

IPC: G06N3/04 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06N3/04 ,  G06F9/4881 ,  G06F9/5016

Abstract: Embodiments relate to streaming convolution operations in a neural processor circuit that includes a neural engine circuit and a neural task manager. The neural task manager obtains multiple task descriptors and multiple subtask descriptors. Each task descriptor identifies a respective set of the convolution operations of a respective layer of a set of layers. Each subtask descriptor identifies a corresponding task descriptor and a subset of the convolution operations on a portion of a layer of the set of layers identified by the corresponding task descriptor. The neural processor circuit configures the neural engine circuit for execution of the subset of the convolution operations using the corresponding task descriptor. The neural engine circuit performs the subset of the convolution operations to generate output data that correspond to input data of another subset of the convolution operations identified by another subtask descriptor from the list of subtask descriptors.

公开(公告)号：US20220083369A1

公开(公告)日：2022-03-17

申请号：US17143149

申请日：2021-01-06

Applicant: Apple Inc.

Inventor： Michael D. Snyder ,  Ronald P. Hall ,  Deepak Limaye ,  Brett S. Feero ,  Rohit K. Gupta

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/54

Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

公开(公告)号：US20230368008A1

公开(公告)日：2023-11-16

申请号：US17745032

申请日：2022-05-16

Applicant: Apple Inc.

Inventor： Sayyed Karen Khatamifard ,  Alexander J. Kirchhoff ,  Rohit K. Gupta ,  Jeffrey D. Marker ,  Thomas G. Anderl ,  Saman Naderiparizi ,  Chenfan Sun ,  Alon Yaakov ,  Husam Khashiboun ,  Ramana V. Rachakonda

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: Embodiments relate to streaming operations in a neural processor circuit that includes a neural engine circuit and a data processor circuit. The neural engine circuit performs first operations on a first input tensor of a first layer to generate a first output tensor, and second operations on a second input tensor of a second layer at a higher hierarchy than the first layer, the second input tensor corresponding to the first output tensor. The data processor circuit stores a portion of the first input tensor for access by the neural engine circuit to perform a subset of the first operations and generate a portion of the first output tensor. The data processor circuit stores the portion of the first output tensor for access by the neural engine circuit as a portion of the second input tensor to perform a subset of the second operations.

公开(公告)号：US11704245B2

公开(公告)日：2023-07-18

申请号：US17462777

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.