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公开(公告)号：US20200371974A1
公开(公告)日：2020-11-26
申请号：US16872595
申请日：2020-05-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby , Andrew J. Berkley , Christopher B. Rich
Abstract: A quantum processor performs input and output which may be performed synchronously. The quantum processor executes a problem to generate a classical output state, which is read out at least partially by an I/O system. The I/O system also transmits a classical input state to by the I/O system, which may include the same qubit-proximate devices used for read-out. The classical input state is written to the qubits, and the quantum processor executes based on the classical input state (e.g., by performing reverse annealing to transform the classical input state to quantum state).
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公开(公告)号：US12034404B2
公开(公告)日：2024-07-09
申请号：US17158484
申请日：2021-01-26
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew J. Berkley , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker , Paul I. Bunyk , Peter D. Spear , Christopher B. Rich
CPC classification number: H03B15/003 , G06N10/20 , G06N10/40 , H01P7/08 , H01P7/105 , H03H7/01 , H10N60/12 , G06N10/00 , H03B2201/02
Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
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13.发明公开公开(公告)号：US20230143506A1
公开(公告)日：2023-05-11
申请号：US17399375
申请日：2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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Patent Agency Ranking
公开(公告)号：US20210218367A1
公开(公告)日：2021-07-15
申请号：US17158484
申请日：2021-01-26
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew J. Berkley , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker , Paul I. Bunyk , Peter D. Spear , Christopher B. Rich
Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
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公开(公告)号：US20210057631A1
公开(公告)日：2021-02-25
申请号：US16996595
申请日：2020-08-18
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , George E.G. Sterling , Christopher B. Rich
Abstract: Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.
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公开(公告)号：US20200379768A1
公开(公告)日：2020-12-03
申请号：US16854396
申请日：2020-04-21
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew J. Berkley , Ilya V. Perminov , Mark W. Johnson , Christopher B. Rich , Fabio Altomare , Trevor M. Lanting
IPC: G06F9/38 , G06F16/901 , G06N10/00
Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.
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17.发明授权Systems and methods for improving the performance of a quantum processor by reducing errors 有权通过减少误差来提高量子处理器性能的系统和方法公开(公告)号：US09495644B2
公开(公告)日：2016-11-15
申请号：US14340303
申请日：2014-07-24
Applicant: D-WAVE SYSTEMS INC.
Inventor： Fabian Ariel Chudak , Christopher B. Rich , Paul I. Bunyk
CPC classification number: G06N99/002 , B82Y10/00
Abstract: Techniques for improving the performance of a quantum processor are described. Some techniques employ improving the processor topology through design and fabrication, reducing intrinsic/control errors, reducing thermally-assisted errors and methods of encoding problems in the quantum processor for error correction.
Abstract translation: 描述了用于改善量子处理器的性能的技术。 一些技术通过设计和制造来改进处理器拓扑，减少内在/控制误差，减少热辅助误差和量子处理器中编码问题的方法进行纠错。
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18.发明申请SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF A QUANTUM PROCESSOR BY REDUCING ERRORS 有权通过减少误差来提高量子处理器的性能的系统和方法公开(公告)号：US20150032994A1
公开(公告)日：2015-01-29
申请号：US14340303
申请日：2014-07-24
Applicant: D-WAVE SYSTEMS INC.
Inventor： Fabian Ariel Chudak , Christopher B. Rich , Paul I. Bunyk
CPC classification number: G06N99/002 , B82Y10/00
Abstract: Techniques for improving the performance of a quantum processor are described. Some techniques employ improving the processor topology through design and fabrication, reducing intrinsic/control errors, reducing thermally-assisted errors and methods of encoding problems in the quantum processor for error correction.
Abstract translation: 描述了用于改善量子处理器的性能的技术。 一些技术通过设计和制造来改进处理器拓扑，减少内在/控制误差，减少热辅助误差和量子处理器中编码问题的方法进行纠错。
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