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公开(公告)号：FR2740598A1
公开(公告)日：1997-04-30
申请号：FR9612695
申请日：1996-10-18
Applicant: FUJITSU LTD
Inventor： TAJIMA MASAYA , UEDA TOSHIO , KURIYAMA HIROHITO , ISHIDA KATSUHIRO , YAMAMOTO AKIRA
Abstract: The display panel has a sub-frame selector receiving the vertical synchronisation signal to determine the number of sub-frames that can be displayed. A display controller (35) is connected to the sub-frame selector and uses the sub-frame selection to determine the data content of each sub-frame. The controller numbers the sub-frames and a counter delivers the number of the sub-frame currently being displayed. The display driver then delivers the appropriate grey scale image for that sub-frame. The incoming signal is then rescaled by altering the number of bits to a new grey scale. The number of bits chosen depends on the display frequency required.
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公开(公告)号：DE69409760T2
公开(公告)日：1999-05-27
申请号：DE69409760
申请日：1994-01-31
Applicant: FUJITSU LTD
Inventor： FUJISAKI TAKASHI , OTSUKA AKIRA , UEDA TOSHIO , TOMIO SIGETOSHI , TAJIMA MASAYA
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公开(公告)号：FR2752633A1
公开(公告)日：1998-02-27
申请号：FR9714356
申请日：1997-11-17
Applicant: FUJITSU LTD
Inventor： ISHIDA KATSUHIRO , UEDA TOSHIO , TAJIMA MASAYA , OTOBE YUKIO , YOSHIDA MASAHIRO , OTAKA NOBUAKI
IPC: H04N5/66 , G06T5/00 , G09G3/20 , G09G3/28 , G09G3/296 , G09G5/37 , H04N1/405 , H04N1/41 , H04N5/70 , H04N9/30 , G09F9/313 , H04N1/52
Abstract: An image processing device has an error distribution unit, and a multiplier. The error distribution unit carries out an error distribution operation to artificially increase the number of shades to be displayed on a display. The multiplier multiplies an input signal by a multiplication coefficient, so that the input signal is separated into display data and error data along a bit boundary and the error distribution operation is carried out on the input signal. Further, a semiconductor integrated circuit has a dither pattern generator, an adder, and an error distribution unit. The dither pattern generator stores a plurality of dither patterns in advance and receives an input image signal, the adder receives the input image signal and a pattern signal from the dither pattern generator, and the error distribution unit carries out an error distribution operation on the output of the adder. Therefore, the image processing device can realize a smooth display characteristic for the entire range of input shades.
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公开(公告)号：FR2744276A1
公开(公告)日：1997-08-01
申请号：FR9608409
申请日：1996-07-05
Applicant: FUJITSU LTD
Inventor： TOMIO SHIGETOSHI , KANAZAWA YOSHIKAZU , KISHI TOMOKATSU , SAKAMOTO TETSUYA , YAMAMOTO AKIRA , TAJIMA MASAYA , UEDA TOSHIO , KURIYAMA HIROHITO , ISHIDA KATSUHIRO
Abstract: The plasma display apparatus includes a plasma display panel with a series of selectively dischargeable and light radiation cells. A reset device resets all of the cells to a predetermined state. An addresser sets the cells to states corresponding to display data. A sustaining discharger causes the cells to radiate light according to the states. An operation stop detector detects occurrences of an operation stop of the plasma display panel. An initialiser initialise all of the cells when the plasma display panel stops its operation. A waveform generating circuit generates waveforms based on waveform data and control data for generating the waveforms stored in a ROM. ROM data is divided into basic cycle data which changes with a basic cycle and long cycle data which changes with long cycles, whose lengths are some times of that of the basic cycle, and the basic cycle data and the long cycle data are respectively stored in the ROM. The basic cycle data and long cycle data are respectively read from the ROM with the corresponding cycles and they are respectively used to generate basic cycle waveforms and long cycle waveforms.
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公开(公告)号：DE69630929T2
公开(公告)日：2004-05-19
申请号：DE69630929
申请日：1996-08-05
Applicant: FUJITSU LTD
Inventor： ISHII TOMOYUKI , HIROSE TADATSUGU , KANAZAWA YOSHIKAZU , UEDA TOSHIO , KISHI TOMOKATSU , TOMIO SHIGETOSHI , ASAMI FUMITAKA
IPC: G09G3/20 , G09G3/292 , G09G3/293 , G09G3/294 , G09G3/296 , G09G3/298 , G09G3/299 , H01J17/49 , G09G3/28
Abstract: An electrode drive circuit (22-27) performs interlaced scanning, ensuring that the phases of the sustaining pulse in odd-numbered lines and even-numbered lines L1 to L8 formed between surface discharge electrodes (X1 to X5, Y1 to Y4) are opposite to each other. When either odd-numbered lines or even-numbered lines are displayed, the voltages applied between the electrodes of the undisplayed lines are at zero, eliminating the necessity for partitioning walls for the surface discharge electrodes. Pairs of X electrodes are provided on respective upper and lower sides of a Y electrode. The areas between the Y and X electrodes on the upper sides are assigned to be display lines for odd-numbered frames, and the areas between the Y and X electrodes on the lower sides are assigned to be display lines for even-numbered frames. Alternate areas between the surface discharge electrodes are assigned as blind lines and a discharge light emission in the blind lines is blocked or incident light to the blind lines from the outside is absorbed. Address electrodes (A1 to A6) are provided for each monochromatic pixel column and selectively connected with the pads above them, performing simultaneous selection of lines.
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Patent Agency Ranking
公开(公告)号：FR2781966B1
公开(公告)日：2003-08-15
申请号：FR9902873
申请日：1999-03-09
Applicant: FUJITSU LTD
Inventor： MIKOSHIBA SHIGEO , SHIGA TOMOKAZU , ZHU YIWEN , IGARASHI KIYOSHI , TODA KOSAKU , UEDA TOSHIO , KARIYA KYOJI
Abstract: A halftone display method utilizes an activation sequence having a plurality of luminance blocks predefined in each frame or field to display an image and having redundancy that enables one gray-scale level to be expressed by any one of a plurality of combinations of subframes (luminance blocks). When determining luminance blocks for use to display gray scale of an arbitrary first pixel, the luminance blocks to be used for the first pixel are selected in accordance with a predetermined rule, based on how the luminance blocks are used for a second pixel located in close proximity to the first pixel. In this way, by actively utilizing the redundancy of the activation sequence, the occurrence of moving-image false contours (false color contours) in video can be minimized, and also a motion compensation equalizing pulse method can be effectively applied to further improve the image display quality.
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公开(公告)号：FR2733070B1
公开(公告)日：2000-07-28
申请号：FR9603436
申请日：1996-03-20
Applicant: FUJITSU LTD
Inventor： ISHIDA KATSUHIRO , UEDA TOSHIO , TAJIMA MASAYA , OTOBE YUKIO , YOSHIDA MASAHIRO , OTAKA NOBUAKI
IPC: H04N5/66 , G06T5/00 , G09G3/20 , G09G3/28 , G09G3/296 , G09G5/37 , H04N1/405 , H04N1/41 , H04N5/70 , H04N9/30 , G09F9/313 , H04N1/52
Abstract: An image processing device has an error distribution unit, and a multiplier. The error distribution unit carries out an error distribution operation to artificially increase the number of shades to be displayed on a display. The multiplier multiplies an input signal by a multiplication coefficient, so that the input signal is separated into display data and error data along a bit boundary and the error distribution operation is carried out on the input signal. Further, a semiconductor integrated circuit has a dither pattern generator, an adder, and an error distribution unit. The dither pattern generator stores a plurality of dither patterns in advance and receives an input image signal, the adder receives the input image signal and a pattern signal from the dither pattern generator, and the error distribution unit carries out an error distribution operation on the output of the adder. Therefore, the image processing device can realize a smooth display characteristic for the entire range of input shades.
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公开(公告)号：FR2738377B1
公开(公告)日：1998-10-30
申请号：FR9606721
申请日：1996-05-31
Applicant: FUJITSU LTD
Inventor： KURIYAMA HIROHITO , TAJIMA MASAYA , UEDA TOSHIO , ISHIDA KATSUHIRO , YAMAMOTO AKIRA
Abstract: A panel display has a display panel including a plurality of cells to be selectively discharged to an address driver for setting the plurality of cells to states represented by display data. The panel display also has a display glowing driver for enabling the plurality of cells to glow according to the set states. One frame during which one screen is displayed has a plurality of sub-frames and glowing periods within the sub-frames, during which the display cells are enabled to glow by the display glowing driver. The said sub-frames are weighted in order to achieve gray-scale display. The display panel also has a display load calculating circuit for calculating a display load to be imposed on a whole display surface during each sub-frame. In addition, a corrected period calculating circuit calculates a corrected period of a glowing period, during which the display cells are enabled to glow by the display glowing driver according to display loads to be imposed during each sub-frame. This is calculated by the display load calculating circuit so that brightness attained by the display cells during respective sub-frames will be maintained at a given ratio.
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公开(公告)号：FR2760121A1
公开(公告)日：1998-08-28
申请号：FR9710796
申请日：1997-08-29
Applicant: FUJITSU LTD
Inventor： KANAZAWA YOSHIKAZU , UEDA TOSHIO
IPC: G09G3/20 , G09G3/288 , G09G3/296 , G09G3/298 , H01J11/12 , H01J11/22 , H01J11/24 , H01J11/26 , H01J11/28 , H01J11/34 , H01J11/36 , H01J11/38 , H01J11/42 , H01J11/44 , H04N5/66 , G09G3/28 , G09F9/313 , H01J17/49
Abstract: The display panel has two substrates (21,28) with electrodes (11,12) placed parallel to each other on one of the substrates. A discharge gas fills the space between the substrates. A control circuit (102-105) applies controlled potentials to the electrodes. A screen (40-43) blocks part of the light emitted by the display lines at edges of the display. Each display line is formed between two adjacent electrodes, with the control signals applied so that a discharge is generated between the electrodes to generate a display line.
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公开(公告)号：FR2740253B1
公开(公告)日：1998-06-19
申请号：FR9612984
申请日：1996-10-24
Applicant: FUJITSU LTD
Inventor： OTOBE YUKIO , YOSHIDA MASAHIRO , OTAKA NOBUAKI , TAJIMA MASAYA , ISHIDA KATSUHIRO , OGAWA KIYOTAKA , UEDA TOSHIO
IPC: G09G3/20 , G09G3/282 , H04N5/66 , G09G3/288 , G09G3/291 , G09G3/294 , G09G3/298 , G09G5/399 , G09G3/28 , H01J17/49
Abstract: A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF1 through SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance level 0 to a luminance level N.
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