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公开(公告)号：AU612076B2
公开(公告)日：1991-06-27
申请号：AU5453890
申请日：1990-04-27
Applicant: FUJITSU LTD
Inventor： NOJIMA SATOSHI , TAKEYAMA AKIRA , TOMINAGA SUSUMU , TSUBOI MITSURU
IPC: H04L49/111 , H04L12/56
Abstract: A packet switching system having a matrix switch including input packet transfer buses (61 - 6n) and output packet transfer buses (81 - 8n). Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.
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公开(公告)号：CA2015514A1
公开(公告)日：1991-02-22
申请号：CA2015514
申请日：1990-04-26
Applicant: FUJITSU LTD
Inventor： TSUBOI MITSURU , TOMINAGA SUSUMU , TAKEYAMA AKIRA , NOJIMA SATOSHI
Abstract: A packet switching system having a matrix switch including input packet transfer buses (61 - 6n) and output packet transfer buses (81 - 8n). Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.
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公开(公告)号：AU8100287A
公开(公告)日：1988-05-06
申请号：AU8100287
申请日：1987-10-16
Applicant: FUJITSU LTD
Inventor： NOJIMA SATOSHI , SAKAGAWA KAZUO , SUZUKI HIDEO
IPC: G06F13/42
Abstract: A data transfer system having a transfer discrimination circuit for discriminating the type of data transfer between an input/output channel device and I/O devices for a computer includes a transfer discrimination circuit. This circuit includes a edge detection unit operating in response to a tag signal supplied to the edge detection unit for detecting the trailing edge of the tag signal after a leading edge of the tag signal has passed. The edge detection unit having a leading edge detector, a trailing edge detector, a storage element, and logic gate circuits. A timing unit is included operating in response to the output of the edge detection unit for counting a predetermined time, along with a discrimination storage unit operating in response to the output of the timing unit for delivering an output indicating an interlock data transfer or an output indicating a data streaming feature data transfer.
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公开(公告)号：AU1814183A
公开(公告)日：1984-03-08
申请号：AU1814183
申请日：1983-08-19
Applicant: FUJITSU LTD
Inventor： TAKEYAMA AKIRA , TAZAKI KENSHI , NOJIMA SATOSHI , ARITAKE NORIHIRO , MITA TERUYOSHI
Abstract: @ A loop transmission system comprises a plurality of node stations (ND-A...ND-D), a supervisory station (SV), and two duplicate loop transmission lines (TL1, TL2) which transmit signals in opposite directions. In operation of the system, the supervisory station sends out loop-back commands (LB-0 ON, LB-1 ON) via both of the duplicate loop transmission lines when faults are detected on both of the transmission lines at the same time. Upon receipt of a loop-back command, each of the node stations establishes a loop-back path (TLC) while retaining a connection path to a succeeding note station. The supervisory station then sends release commands (LB-0 OFF, LB-1 OFF) to the node stations, and the loop-back path is released only in those node stations which receive signals normally from both of the duplicate loop transmission lines.
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公开(公告)号：CA2038458C
公开(公告)日：1999-01-26
申请号：CA2038458
申请日：1991-03-18
Applicant: FUJITSU LTD
Inventor： TOMINAGA SUSUMU , NOJIMA SATOSHI
IPC: H04L12/701 , H04L12/721 , H04Q3/42 , H04L12/56
Abstract: In a network, a route which can be uniquely identified is constructed by selecting an arbitrary packet-switching node and an arbitrary transmission line in an arbitrary order from the network. A route memory unit stores data indicating which route is involved in which transmission line within the network. A congested state detecting unit detects a congested state of a transmission line accommodated within its own node. The detected congested state is transmitted to another node by a congested state informing unit as congested state information. A route identifying unit receives the congested state information from the other node and retrieves a route within a corresponding transmission line from the route memory unit to thereby identify the route accommodated within its node. A route control unit carries out control of the congested state of the identified route on the basis of the received congested state information. As described above, since traffic passing the transmission line is classified into "route" and grouped, an object whose congestion is to be supervised is limited and each node can regulated only the traffic passing the transmission line in which the congestion occurred in units of routes.
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Patent Agency Ranking
公开(公告)号：DE69032699D1
公开(公告)日：1998-11-19
申请号：DE69032699
申请日：1990-04-27
Applicant: FUJITSU LTD
Inventor： TSUBOI MITSURU , TOMINAGA SUSUMU , TAKEYAMA AKIRA , NOJIMA SATOSHI
IPC: H04L49/111 , H04L12/56
Abstract: A packet switching system having a matrix switch including input packet transfer buses (61 - 6n) and output packet transfer buses (81 - 8n). Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.
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公开(公告)号：DE3788721T2
公开(公告)日：1994-06-09
申请号：DE3788721
申请日：1987-10-16
Applicant: FUJITSU LTD
Inventor： NOJIMA SATOSHI , SAKAGAWA KAZUO , SUZUKI HIDEO
IPC: G06F13/42
Abstract: A data transfer system having a transfer discrimination circuit for discriminating the type of data transfer between an input/output channel device and I/O devices for a computer includes a transfer discrimination circuit. This circuit includes a edge detection unit operating in response to a tag signal supplied to the edge detection unit for detecting the trailing edge of the tag signal after a leading edge of the tag signal has passed. The edge detection unit having a leading edge detector, a trailing edge detector, a storage element, and logic gate circuits. A timing unit is included operating in response to the output of the edge detection unit for counting a predetermined time, along with a discrimination storage unit operating in response to the output of the timing unit for delivering an output indicating an interlock data transfer or an output indicating a data streaming feature data transfer.
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公开(公告)号：CA1196976A
公开(公告)日：1985-11-19
申请号：CA434837
申请日：1983-08-17
Applicant: FUJITSU LTD
Inventor： TAKEYAMA AKIRA , TAZAKI KENSHI , NOJIMA SATOSHI , ARITAKA NORIHIRO , MITA TERUYOSHI
Abstract: LOOP TRANSMISSION SYSTEM AND METHOD OF CONTROLLING THE LOOP-BACK CONDITION THEREOF A loop transmission system and a method of controlling the loop-back condition thereof. The loop transmission system comprises a plurality of node stations, a supervisory station, and two duplicate loop transmission lines which transmit signals in opposite directions. In the loop transmission system, the supervisory station first sends out loop-back commands via both of the duplicate loop transmission lines when faults are detected on both of the duplicate loop transmission lines at the same time. Each of the node stations establishes a loop-back path while retaining a connection path to a succeeding node station upon the receipt of a loop-back command. The loop-back path is released only in the node stations which receive signals normally from both of the duplicate loop transmission lines when the supervisory station sends release commands to the node stations after sending the loopback commands.
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公开(公告)号：AU542693B2
公开(公告)日：1985-03-07
申请号：AU1814183
申请日：1983-08-19
Applicant: FUJITSU LTD
Inventor： TAKEYAMA AKIRA , TAZAKI KENSHI , NOJIMA SATOSHI , ARITAKE NORIHIRO , MITA TERUYOSHI
Abstract: @ A loop transmission system comprises a plurality of node stations (ND-A...ND-D), a supervisory station (SV), and two duplicate loop transmission lines (TL1, TL2) which transmit signals in opposite directions. In operation of the system, the supervisory station sends out loop-back commands (LB-0 ON, LB-1 ON) via both of the duplicate loop transmission lines when faults are detected on both of the transmission lines at the same time. Upon receipt of a loop-back command, each of the node stations establishes a loop-back path (TLC) while retaining a connection path to a succeeding note station. The supervisory station then sends release commands (LB-0 OFF, LB-1 OFF) to the node stations, and the loop-back path is released only in those node stations which receive signals normally from both of the duplicate loop transmission lines.
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公开(公告)号：JPH0448303B2
公开(公告)日：1992-08-06
申请号：JP24442385
申请日：1985-10-31
Applicant: FUJITSU LTD
Inventor： TSUTSUI HIDEKAZU , KAZETANI KYOSHI , NOJIMA SATOSHI
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