公开(公告)号：US20150115284A1

公开(公告)日：2015-04-30

申请号：US14396852

申请日：2013-05-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Kevin Sean Matocha ,  Richard Joseph Saia ,  Zachary Matthew Stum ,  Ljubisa Dragoljub Stevanovic ,  Kuna Venkat Satya Rama Kishore ,  James William Kretchmer

IPC: H01L29/36 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/0638 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613

Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.

Abstract translation: 半导体器件包括：包含碳化硅的衬底; 设置在所述衬底上的漂移层，包括掺杂有第一掺杂剂和导电类型的漂移区; 以及掺杂有第二掺杂剂和导电类型的第二区域，其邻近漂移区并且靠近漂移层的表面。 所述半导体器件还包括与所述第二区相邻的连接终端延伸部，所述连接终端延伸部具有在掺杂有不同浓度的所述第二掺杂剂类型的第一和第二方向上分离的宽度和离散区域以及所述第二导电类型的功能形式的有效掺杂分布 这通常从主阻塞结的边缘减小。 宽度小于或等于一维耗尽宽度宽度的五倍的倍数，半导体器件的电荷容差大于1.0×1013 / cm2。

公开(公告)号：US20140361315A1

公开(公告)日：2014-12-11

申请号：US14467754

申请日：2014-08-25

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Zachary Matthew Stum ,  Stephen Daley Arthur ,  Kevin Sean Matocha ,  Peter Almern Losee

IPC: H01L29/36 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/36 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7816 ,  H01L29/7827

Abstract: A semiconductor device according to one embodiment having a first region comprising a first dopant type, a second region adjacent the first region haivng a second dopant type and a channel region. There is a third region segregated from the channel region having a second dopant type, wherein the third region substantially coincides with the second region.

Abstract translation: 根据一个实施例的半导体器件具有包括第一掺杂剂类型的第一区域，与第二掺杂剂类型的第一区域相邻的第二区域和沟道区域。 存在与具有第二掺杂剂类型的沟道区隔开的第三区域，其中第三区域基本上与第二区域重合。

公开(公告)号：US08507986B2

公开(公告)日：2013-08-13

申请号：US13740758

申请日：2013-01-14

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Zachary Matthew Stum ,  Peter Almren Losee ,  James Jay McMahon

IPC: H01L29/76 ,  H01L21/332

CPC classification number: H01L27/088 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

Abstract translation: 在一个实施例中，本发明包括一个包含单个MOSFET单元的MOSFET。 每个单元包括形成在井内的U形孔（P型）和两个平行的源（N型）。 在多个位置连接多个源极（掺杂N）源极。 两个梯级之间的区域包括一个主体（P型）。 这些特征形成在形成在N型衬底上的N型外延层上。 联系人跨越并接触许多源级和身体。 栅极氧化物和栅极接触覆盖第一阱的支腿和第二相邻阱的支路，响应于栅极电压而反转导电性。 MOSFET包括多个这些单元以获得期望的低通道电阻。 在制造过程的几个状态下使用自对准技术形成单元区域。

公开(公告)号：US20130146898A1

公开(公告)日：2013-06-13

申请号：US13740734

申请日：2013-01-14

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

IPC: H01L29/49

CPC classification number: H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

Abstract: The present application provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

Abstract translation: 本申请提供了制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极触点与源极之间的距离小于0.6μm。 还提供了一个垂直的SiC MOSFET。