公开(公告)号：US12057444B2

公开(公告)日：2024-08-06

申请号：US17808364

申请日：2022-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Souvick Mitra ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Meng Miao ,  Anindya Nath ,  Wei Liang

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7436

Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

公开(公告)号：US20220115864A1

公开(公告)日：2022-04-14

申请号：US17068967

申请日：2020-10-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anindya Nath ,  Zhiqing Li ,  Souvick Mitra ,  Alain Loiseau ,  Wei Liang

IPC: H02H9/04 ,  H01L27/02

Abstract: Embodiments of the disclosure provide an electrostatic discharge (ESD) device, including: an input pad; an underlapped field effect transistor (UL-FET) with a trigger voltage Vt, including: an underlapped drain region coupled to the input pad; a source region coupled to ground; and a gate structure coupled to the input pad; and a blocking layer separating the underlapped drain region from the gate structure of the UL-FET by an underlap distance.